Power Optimization of Combinational Quaternary Logic Circuits

Abstract

Due to the need of interconnections design of binary circuits is limited. Interconnection increases area, delay and energy consumption in CMOS digital circuits. A possible solution could be here as, in the same chip area we use more sets of signals. Multiple value logic can decrease average power required for level transitions and reduces the number of necessary interconnections. In this paper we design various combinational modules using Quaternary logic. Various combinational circuits are Quaternary full adder using unique encoding, quaternary encoder & decoder and quaternary multiplexer. These designs are aimed to reduce the transistors used in the implementation of circuits and reducing the power dissipation. Power optimization is achieved using MTCMOS technique. Simulation has been done in Tanner 13 EDA tool on BSIM3 180nm CMOS technology. KeywordsMulti value logic, power optimization, quaternary full adder, quaternary encoder & decoder, quaternary multiplexer and MTCMOS technique. __________________________________________________*****_________________________________________________