Quasi-floating Gate Transistors Research Articles

Effect of ionizing radiation on quasi-floating gate transistors

Low power and low voltage are key in modern design. The quasi-floating gate (QFG) has proven to be an adequate choice in numerous applications. However, so far, its use has not spread in high-radiation environments because of the lack of studies on the performance of this technique under radiation. This work addresses the effect of ionizing radiation in the QFG transistor. To this end, a specific DUT has been designed and irradiated up to 2,25 Mrad. The experimental results show a tolerable reduction in the equivalent resistivity of the pseudoresistor (a reverse biased n-well PN junction). The effect is due to the increase in the reverse saturation current of the diode present between the pseudoresistor’s terminals, which is consistent with Displacement Damage Dose (DDD).

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.

Analog CMOS Readout Channel for Time and Amplitude Measurements With Radiation Sensitivity Analysis for Gain-Boosting Amplifiers

The front-end readout channel consists of a charge sensitive amplifier (CSA) and two different unipolar-shaping circuits to generate pulses suitable for time and energy measurement. The signal processing chain of the single channel is built of two different parallel processing paths: a fast path with a peaking time of 30 ns to obtain the time of arrival for each particle impinging the detector; and a slow path with a peaking time of 400 ns dedicated for low noise amplitude measurements, which is formed by a pole-zero cancellation circuit and a 4th order complex shaper based on a bridged-T architecture. The tunability of the system is accomplished by the discharge time constant of the CSA in order to accommodate various event rates. The readout system has been implemented in a 180 nm CMOS technology with the size of 525 μm x 290 μm. The building blocks use compact gain-boosting techniques based on quasi-floating gate (QFG) transistors achieving accurate energy measurement with good resolution. The high impedance nodes of QFG transistors require a detailed study of sensitivity to single-effect transients (SET). After carrying out this study, this paper proposes a method to select the value of the QFG capacitors, minimizing the area occupancy while maintaining robustness to radiation. The nonlinearity of the CSA-slow-shaper has been found to be less than 1% over a 10-70 fC input charge. The power dissipation of the readout channel is 4.1 mW with a supply voltage of 1.8 V.

An Op-Amp Approach for Bandpass VGAs With Constant Bandwidth

Two approaches to implement variable gain amplifiers based on Miller op-amps are discussed. One has true constant bandwidth while the other has essentially reduced bandwidth variations with varying gain. Servo-loops and ac coupling techniques with quasi floating gate transistors are used to provide a bandpass response with very low cutoff frequency in the range of hertz. In practice, one of the schemes is shown to have bandwidth variations close to a factor two while the second one has true constant bandwidth over the gain tuning range. Experimental results of test chip prototypes in 180-nm CMOS technology verify the theoretical claims.

High gain amplifier with feedforward compensation based on quasi-floating gate transistors

In this paper, a two-stage amplifier with feedforward frequency compensation scheme is presented. Because the frequency compensation scheme uses the amplifier's second stage gm to create the feedforward path no additional circuitry is needed. To verify the proposed scheme a prototype was fabricated using 0.5μm technology. Measurements results demonstrate a high DC gain, 18MHz of gain-bandwidth product and 86° phase margin are achieved with an output load capacitance of 80pF.

Low-Power Analog Channel Selection Filtering Techniques

Various techniques to reduce power consumption in the channel selection filtering of wireless receivers are discussed. They include class AB operation by the use of quasi-floating gate transistors and reuse of circuital blocks. A mixed continuous/discrete frequency tuning approach set by a simple on-chip automatic tuning circuit is also presented, which allows wide tuning range with modest area and power requirements. The techniques presented are illustrated by a third-order CMOS Gm-C channel filter designed for a dual-mode Bluetooth/ZigBee zero-IF receiver, with two different on-chip automatic tuning circuits. Measurement results for a test chip prototype in a 0.5- $${\upmu }$$μm CMOS process are presented, showing in-band filter IIP3 >20 dBVp with a power consumption of 3.65 mW for both Bluetooth and ZigBee modes, and the required frequency tuning range set by the automatic tuning circuits.

Design of CMOS amplifiers with offset rejection using positive-feedback QFG transistors

Two novel complementary design techniques of very-low DC gain CMOS amplifiers are presented. They are based on two classical positive-feedback structures for gain enhancement, increasing the equivalent load resistance and the transconductance of the input differential pair respectively. Quasi-Floating Gate transistors have been employed for designing frequency-dependent structures that reduce strongly the amplifier gain in DC and at very low frequencies, allowing the conventional high gain at frequencies starting at a few Hz. These broadband features make the proposed design techniques suitable for applications where weak input signals with large DC offset voltages have to be handled, such as biomedical signal processing or direct conversion communication receivers. Both ideas have been applied to simple one stage OTAs that have been fabricated in a 0.5 μm n-well technology. Measurement results are provided for validating the proposed techniques.

Low voltage linear tunable transconductor for high speed filters

A novel low voltage tunable linear transconductor is presented. The approach is based on quasi-floating gate transistors achieving higher transconductance and better dc common mode rejection than previous implementations. A dynamic biasing technique improves the sensibility of the linearity to process variations. Measurement results of the circuit, designed in a 0.5 μm CMOS process from 1.4 V power supply, confirm the advantages of the proposed approach with a very high speed operation of 50 MHz of gain-bandwidth product, a IM3 of ?40 dB and a nominal power consumption of only 490 μW.

Highly linear micropower class AB current mirrors using Quasi-Floating Gate transistors

A design approach to achieve low-voltage micropower class AB CMOS cascode current mirrors is presented. Both class AB operation and dynamic cascode biasing are based on the use of Quasi-Floating Gate transistors. They allow high linearity for large signal currents and accurately set quiescent currents without requiring extra power consumption or supply voltage requirements. Measurement results show that dynamic cascode biasing allows a wider input range and a linearity improvement of more than 23dB with respect to the use of conventional biasing. A THD value better than −35dB is measured for input amplitudes up to 100 times the bias currents. Two class AB current mirror topologies are proposed, with slightly different ways to achieve class AB operation and dynamic biasing. The proposed current mirrors, fabricated in a 0.5µm CMOS technology, are able to operate with a supply voltage of 1.2V and a quiescent power consumption of only 36µW, using a silicon area <0.025mm2.

Micropower Class-AB VGA With Gain-Independent Bandwidth

A novel class-AB variable gain amplifier with constant bandwidth and continuous gain tuning is presented. It is based on the cascade connection of a tunable transconductor and a transresistance amplifier. Class-AB operation is achieved using quasi-floating gate transistors. The circuit has been fabricated in a 0.5- μm CMOS technology, showing a third-order input intercept point (IIP3) of 13 dBV p for a power consumption of 500 μW.

Tunable Class AB CMOS Gm-C Filter Based on Quasi-Floating Gate Techniques

A tunable CMOS Gm-C channel-select low-pass filter is presented. Class AB operation overcomes the dynamic range versus static power tradeoff of conventional channel-select filter topologies. Programmable transconductors are designed using quasi-floating gate transistors, which provide class AB operation without requiring extra supply voltage or power requirements and keeping accurately set quiescent currents. The filter can be applied to channel selection in highly integrated, low power zero-IF wireless receivers. For example, its frequency tuning range and linearity makes it suitable for a dual-mode Bluetooth/ZigBee zero-IF receiver. Measurement results for a test chip prototype in a 0.5 μm standard CMOS process are presented, showing a THD <; -55 dB for an input of 1.2 Vpp, which corresponds to peak currents 300% larger than the bias current.

Design of micropower class AB transconductors: A systematic approach

A systematic design approach to achieve micropower class AB CMOS transconductors is presented. It includes techniques to get rail-to-rail operation and continuous transconductance tuning, based on floating and Quasi-Floating Gate transistors. Application of the proposed design approach leads to a new family of high-performance power-efficient class AB CMOS transconductors. To illustrate the feasibility of this approach, 12 transconductors derived from this common framework have been designed and fabricated in a 0.5μm CMOS technology. Measurement results show THD values for 2V inputs of −56dB for a static power of 300μW and silicon area <0.07mm2.

DC offset control with application in a zero-IF 0.18 μm CMOS Bluetooth receiver chain

A compact DC offset correction circuit based on the intrinsic properties of quasi-floating gate (QFG) transistors is presented. The proposed scheme uses a tuning mechanism to make its initial response faster improving the traditional large settling time of these circuits. A zero-IF baseband receiver chain suitable for Bluetooth that includes the proposed dc offset correction has been designed in a 0.18 μm CMOS technology at 1.2 V supply voltage.

CMOS triode transconductor based on quasi-floating-gate transistors

A novel CMOS transconductor based on transistors operating in the triode region and quasi-floating gate (QFG) techniques is proposed. The V-I conversion is performed by two triode transistors acting as a current divider and QFG transistors are employed to enforce a constant drain-source voltage, improving the linearity notably. The circuit has been fabricated and measured using a 0.5 µm CMOS technology in order to validate the QFG design.

CMOS buffer using complementary pair of bulk-driven super source followers

A power-efficient rail-to-rail CMOS analogue voltage buffer is presented. It consists of a complementary pair of super source followers, but a bulk-driven input device with the replica-biased scheme is utilised to eliminate the DC level shift, quasi-floating gate transistors to achieve class-AB performance, and a current switch which shifts between the complementary pair to allow rail-to-rail operation. The proposed buffer has been designed for a 0.35 µm CMOS technology to operate at a 1.8 V supply voltage. Simulated results are provided to demonstrate the total harmonic distortion for a 1.6 Vpp 100 kHz sine wave with a 68pF load is as low as −46 dB, while the static current consumption remains under 8 µA.

High performance low-voltage QFG-based DVCC and a novel fully differential SC integrator based on it

This paper proposes a high performance, rail-to-rail, Differential Voltage Current Conveyor (DVCC), using Quasi-Floating Gate (QFG) transistors. With a compact structure, the circuit operates at very low supply voltage (±0.5V), dissipates very low standby power (90µW), has a high bandwidth (f-3dB of 81MHz and 82MHz for Ai and Av, respectively), and a very low input resistance (0.2Ω). Using the proposed DVCC a novel fully differential Switched Capacitor (SC) integrator is also introduced. HSPICE simulation results confirm the functionality of proposed DVCC and integrator.

Very Low Voltage Rail-to-Rail Programmable-Gain CMOS Amplifier

A novel design technique for operating closed-loop amplifier circuits at very low supply voltages is proposed. It is based on the use of quasi-floating gate transistors, avoiding issues encountered in true floating-gate structures such as the initial floating-gate charge, offset drift with temperature, and the gain-bandwidth product degradation. A programmable-gain differential amplifier is designed and implemented following this method. Measurement results of an experimental prototype fabricated in a 0.5-μm CMOS technology validate on silicon the proposed technique.