Design of CMOS amplifiers with offset rejection using positive-feedback QFG transistors

Abstract

Two novel complementary design techniques of very-low DC gain CMOS amplifiers are presented. They are based on two classical positive-feedback structures for gain enhancement, increasing the equivalent load resistance and the transconductance of the input differential pair respectively. Quasi-Floating Gate transistors have been employed for designing frequency-dependent structures that reduce strongly the amplifier gain in DC and at very low frequencies, allowing the conventional high gain at frequencies starting at a few Hz. These broadband features make the proposed design techniques suitable for applications where weak input signals with large DC offset voltages have to be handled, such as biomedical signal processing or direct conversion communication receivers. Both ideas have been applied to simple one stage OTAs that have been fabricated in a 0.5 μm n-well technology. Measurement results are provided for validating the proposed techniques.