Quantum-dot Cellular Automata Research Articles

A novel QCA circuit-switched network with power dissipation analysis for nano communication applications

Today, communication links and networks are essential in transmitting data and information. Moreover, information sharing in communication devices and networks has become necessary, routine, and unavoidable. Consequently, designing and manufacturing high-speed nano-scale devices with ultra-low power consumption is very important. Among the emerging paradigms in nanotechnologies, quantum-dot cellular automata (QCA) is very popular in communication sciences. In the present study, we optimize the design and implementation of a QCA crossbar switch and use it in transmitter and receiver circuits. Subsequently, a circuit-switched network in QCA technology is implemented using these devices. All the designed circuits are coplanar with the minimum number of cells, optimal area and latency, and low power consumptions, which employ standard QCA design rules and show superiority and advantages compared to the previous designs.

3-bit Shift Register Using QCA Nanotechnology

Background:: Quantum-dot Cellular Automata (QCA) is a new emerging nanotechnology that has been proven to be an improved alternative to complementary metal oxide semiconductor (CMOS) technology. It consists of a group of cells that can perform computational functions when combined and arranged in a particular manner. Objective:: The Flip-Flops are widely affiliated with the circuits of logical and arithmetic unit structures that are used for the processors. Data (D) Flip-Flop is the most important and widely used Flip-Flop among all different types due to its better performance and efficiency. Hence, an efficient D Flip-Flop needs to be developed using QCA nanotechnology. Method:: This paper proposes a new design for D Flip-Flop in QCA nanotechnology. The proposed D Flip-Flop has 28 quantum cells and covers an area of 0.03 μm2 . Furthermore, the paper presents a new design for a 3-bit Shift Register using the proposed D Flip-Flops in QCA nanotechnology keeping in mind the importance of the same in storing and transferring multiple bits of data. Result:: The proposed D Flip-Flop and the 3-bit Shift Register are compared with the existing QCAbased designs. The proposed Shift Register has 100 quantum cells and covers an area of 0.11 μm2 . Conclusion:: The comparison concludes that the proposed D Flip-Flop and the 3-bit Shift Register have used a lesser number of QCA cells and covered smaller areas than the previous works. The proposed designs have been designed in a single layer without any crossover.

Analytical method for cell displacement defect quantum-dot cellular automata primitive

Quantum-dot cellular automata (QCA) is an emerging computational paradigm which can overcome scaling limitations of the existing complementary metal oxide semiconductor (CMOS) technology. The existence of defects cannot be ignored, considering the fabrication of QCA devices at the molecular level where it could alter the functionality. Therefore, defects in QCA devices need to be analyzed. So far, the simulation-based displacement defect analysis has been presented in the literature, which results in an increased demand in the corresponding mathematical model. In this paper, the displacement defect analysis of the QCA main primitive, majority voter (MV), is presented and carried out both in simulation and mathematics, where the kink energy based mathematical model is applied. The results demonstrate that this model can also be valid for the displacement defect in QCA MV.

Novel Quantum-Dot Cellular Automata-Based Gate Designs for Efficient Reversible Computing

Reversible logic enables ultra-low power circuit design and quantum computation. Quantum-dot Cellular Automata (QCA) is the most promising technology considered to implement reversible circuits, mainly due to the correspondence between features of reversible and QCA circuits. This work aims to push forward the state-of-the-art of the QCA-based reversible circuits implementation by proposing a novel QCA design of a reversible full adder\full subtractor (FA\FS). At first, we consider an efficient XOR-gate, and based on this, new QCA circuit layouts of Feynman, Toffoli, Peres, PQR, TR, RUG, URG, RQCA, and RQG are proposed. The efficient XOR gate significantly reduces the required clock phases and circuit area. As a result, all the proposed reversible circuits are efficient regarding cell count, delay, and circuit area. Finally, based on the presented reversible gates, a novel QCA design of a reversible full adder\full subtractor (FA\FS) is proposed. Compared to the state-of-the-art circuits, the proposed QCA design of FA\FS reversible circuit achieved up to 57% area savings, with 46% and 29% reduction in cell number and delay, respectively.

QCA-Based Reliable Fundamental Units for Multiplexer-Demultiplexer and D-Flip-Flop

Quantum-dot cellular automata (QCA) is an advanced nanotechnology. It is applied to delineate nanoscale technology-based logic circuits. It can potentially be replaced the complementary metal oxide semiconductor (CMOS) technology. This paper proposes an optimal and single clocked multiplexer (Mux) circuit, which is made with the help of 12 number of QCA cells in QCA nanotechnology. The proposed Mux circuit is designed in such a way that it can be used easily for the design of the demultiplexer (DeMux) and data flip-flop (DFF) circuits. The proposed Mux is easily converted to DeMux by exchanging the input and output terminals only. The effectiveness of the proposed Mux, DeMux, and DFF is examined with the designs that are similar and available in literature using the QCA Designer-E and QCA Pro tools. The design of the proposed Mux is 89.06% fault-tolerant and has decreased the quantum cost by 62.50% as compared to best reported design. Energy measurement plays a key role when designs are operating at nanoscale level. Energy approximation is done with the help of the QCA Pro tool. The proposed designs are more energy efficient compared to the existing works.

Quantum‐dot cellular automata based design for overflow detection in two's complement arithmetic operation

AbstractThis article describes designing a low‐power novel circuit for overflow detection in two's complement arithmetic operations. The quantum‐dot cellular automata (QCA) is employed to achieve the nanoscale design. For designing the circuit of the proposed arithmetic overflow detector, a new layout of the QCA full adder is utilized. Two different designs of arithmetic overflow detectors are outlined in this article. The designs are compared based on latency, cell count, and device area. Based on the comparison, the best design for an arithmetic overflow detector is presented. The circuit cost for all the designs is also shown in this work. Besides, thermal power's effect on the output cell's polarization has also been investigated. The power dissipation of all proposed QCA layouts is estimated.

Nano‐scale design of full adder and full subtractor using reversible logic based decoder circuit in quantum‐dot cellular automata

AbstractThis paper presents a reversible nano‐scale decoder circuit. The decoder is designed by utilizing the new quantum‐dot cellular automata (QCA) format of the QCA1 gate. This QCA1 gate provides 34.25% less cell count with 54.37% less area than the best existing designs. Thus, the proposed QCA1 gate provides less area considering the best existing state‐of‐the‐art plans. The IBMQ‐based quantum realization of the QCA1 gate is also illustrated. The reversible full adder and subtractor circuits by employing the proposed decoder are likewise explored in this paper. A four‐input reversible OR‐gate is structured and concatenates with a decoder circuit to frame the circuit for full adder and subtractor. The energy dissipation by these QCA circuits is assessed to build up that QCA is an attractive option to CMOS for realizing reversible logic designs. The implemented results are compared with the truth table to ensure operational accuracy. The planned circuits can be utilized to structure reversible designs for nano‐communication.

Design of Cost-Efficient SRAM Cell in Quantum Dot Cellular Automata Technology

SRAM or Static Random-Access Memory is the most vital memory technology. SRAM is fast and robust but faces design challenges in nanoscale CMOS such as high leakage, power consumption, and reliability. Quantum-dot Cellular Automata (QCA) is the alternative technology that can be used to address the challenges of conventional SRAM. In this paper, a cost-efficient single layer SRAM cell has been proposed in QCA. The design has 39 cells with a latency of 1.5 clock cycles and achieves an overall improvement in cell count, area, latency, and QCA cost compared to the reported designs. It can therefore be used to design nanoscale memory structures of higher order.

Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

Being one of the promising techniques for future computing systems, quantum-dot cellular automata (QCA)-based circuit design has gained massive interest among researchers due to which numerous QCA-based full adder (FA) circuits have been designed. Due to numerous QCA FA circuits available in the existing literature, researchers find it difficult to invest the time to search, implement, simulate, and analyze QCA FAs to find the best-suited design according to their needs. Existing review articles do not present a complete overview and performance comparison of QCA FAs. Also, the existing articles do not include quite a number of QCA FA designs in the literature review. As a result, a detailed review including all possible QCA FAs becomes essential. Therefore, rather than going for a new QCA FA design, this research aims to aid researchers by providing an extensive literature review and comprehensive study on existing QCA FAs. A total of 47 QCA FAs have been considered for analysis. The QCA FA implementation method and performance parameters are summarized in a tabular manner to provide a quick overview and comparison of the QCA FAs.

Methodology for Automated Design of Quantum-Dot Cellular Automata Circuits

Quantum-dot Cellular Automata (QCA) provide very high scale integration potential, very high switching frequency, and have extremely low power demands, which make the QCA technology quite attractive for the design and implementation of large-scale, high-performance nanoelectronic circuits. However, state-of-the-art QCA circuit designs were not derived by following a set of universal design rules, as is the case of CMOS circuits, and, as a result, it is either impossible or very difficult to combine QCA circuit blocks in effective large-scale circuits. In this paper, we introduce a novel automated design methodology, which builds upon a QCA specific universal design rules set. The proposed methodology assumes the availability of a generic QCA crossbar architecture and provides the means to customize it in order to implement any given logic function. The programming principles and the flow of the proposed automated design tool for crossbar QCA circuits are described analytically and we apply the proposed automated design method for the design of both combinatorial and sequential circuits. The obtained designs demonstrate that the proposed method is functional, easy to use, and provides the desired QCA circuit design unification.

N譔 Clos Digital Cross-Connect Switch Using Quantum Dot Cellular Automata (QCA)

Quantum dot cellular automata (QCA) technology is emerging as a future technology which designs the digital circuits at quantum levels. The technology has gained popularity in terms of designing digital circuits, which occupy very less area and less power dissipation in comparison to the present complementary metal oxide semiconductor (CMOS) technology. For designing the routers at quantum levels with non-blocking capabilities various multi-stage networks have been proposed. This manuscript presents the design of the N×N Clos switch matrix as a multistage interconnecting network using quantum-dot cellular automata technology. The design of the Clos switch matrix presented in the article uses three input majority gates (MG). To design the 4 × 4 Clos switch matrix, a basic 2 × 2 switch architecture has been proposed as a basic module. The 2 × 2 switching matrix (SM) design presented in the manuscript utilizes three input majority gates. Also, the 2 × 2 SM has been proposed using five input majority gates. Two different approaches (1&2) have been presented for designing 2 × 2 SM using five input majority gates. The 2 × 2 SM design based on three input majority gate utilizes four zone clocking scheme to allow signal transmission. Although, the clocking scheme used in 2 × 2 SM using three input MG and in 2 × 2 SM approach 1 using five input MG is conventional. The 2 × 2 SM approach 2 design, utilizes the clocking scheme in which clocks can be applied by electric field generators easily and in turn the switch element becomes physically realizable. The simulation results conclude that the 2 × 2 SM is suitable for designing a 4 × 4 Clos network. A higher order of input-output switching matrix, supporting more number of users can utilize the proposed designs.

Design Automation for Emerging Technologies

After the continuous development of CMOS technology driven by transistor miniaturization and Moore’s law, the scientific community is witnessing the exploration of emerging paradigms to find new ways to develop computational systems. This paper presents critical concepts for understanding some of these new nanocomputing technologies, specifically field-coupled, quantum-dot cellular automata, nanomagnetic logic, silicon dangling bounds, photonic crystal logic, and DNA computing. Next, it shows emerging design automation tools for each of these areas and how they can be applied to support the development of new computing systems. The level of maturity and production speed of solutions achieved by conventional silicon technology thanks to very efficient electronic design automation (EDA) is remarkable. However, here we are dealing with technologies still in their infancy. Therefore, improvements in design automation tools are undoubtedly a way to accelerate the growth of new substrate alternatives and modern applications.

A Space-Efficient Universal and Multi-Operative Reversible Gate Design Based on Quantum-Dots

Because of the high speed, low-power consumption, low latency and possible use at the atomic and molecular levels, Quantum-dot Cellular Automata (QCA) technology is one of the future nanoscale technologies that can replace the present transistor-based technology. For the purpose of creating QCA circuits, reversible logic can be regarded as an appropriate candidate. In this research, a new structure for multi-operative reversible designs is suggested. The Saeid Nima Gate (SNG), proposed in this research study, is a brand-new, incredibly effective, multi-operative, universal reversible gate implemented in QCA nanotechnology employing both majority and inverter gates. Reversible gates, also known as reversible logic gates, are gates that have n inputs and n outputs, which is an equal number of inputs and outputs. The amount of energy lost during computations will be reduced if the numbers of inputs and outputs are identical. The proposed gate is modified and reorganized to optimize further, employing exact QCA cell interaction. All fundamental logic gates are implemented using it to demonstrate the universality of the proposed SNG. Reversible logic has advanced, and as a result, our suggested solution has a lower quantum cost than previously reported systems. The suggested design is simulated using the QCADesigner-E tools.

A novel design for managing the faults of the 2 × 2 nano-scale crossbar using quantum-dots

Due to new challenges in transistor technology, non-traditional design approaches and processes have risen to the fore. Quantum-dot Cellular Automata (QCA) nano-technology is a fascinating design method that uses columbic repulsion to transmit and manipulate data. On the other hand, crossbar circuits are critical areas in digital circuits and a signal across several users. A new design is suggested in this paper for a crossbar circuit to manage the faults and decrease the complexity. This paper creates the fault-tolerant crossbar circuit by combining a fault-tolerant majority gate. The clock zone technique is used to implement the suggested architecture. As a result, the suggested design is less susceptible to manufacturing flaws. In addition, the proposed design can manage energy dissipation efficiently. QCADesigner-E is used for simulation and energy dissipation studies. The suggested fault-tolerant crossbar circuit in QCA nano-technology has only 156 cells and 0.18 µm2 area.

Multi-Layered QCA Content-Addressable Memory Cell Using Low-Power Electronic Interaction for AI-Based Data Learning and Retrieval in Quantum Computing Environment.

In this study, we propose a quantum structure of an associative memory cell for effective data learning based on artificial intelligence. For effective learning of related data, content-based retrieval and storage rather than memory address is essential. A content-addressable memory (CAM), which is an efficient memory cell structure for this purpose, in a quantum computing environment, is designed based on quantum-dot cellular automata (QCA). A CAM cell is composed of a memory unit that stores information, a match unit that performs a search, and a structure, using an XOR gate or an XNOR gate in the match unit, that shows good performance. In this study, we designed an XNOR gate with a multilayer structure based on electron interactions and proposed a QCA-based CAM cell using it. The area and time efficiency are verified through a simulation using QCADesigner, and the quantum cost of the proposed XOR gate and CAM cell were reduced by at least 70% and 15%, respectively, when compared to the latest research. In addition, we physically proved the potential energy owing to the interaction between the electrons inside the QCA cell. We also proposed an additional CAM circuit targeting the reduction in energy dissipation that overcomes the best available designs. The simulation and calculation of power dissipation are performed by QCADesigner-E and it is confirmed that more than 27% is reduced.

Cost-efficient method for inverter reduction and proper placement in quantum-dot cellular automata

ABSTRACT The Quantum-dot Cellular Automata (QCA), an emerging technology, is observed to be the most viable solution to current CMOS. It is capable of finding solutions to challenges, like high power consumptionand device density. The elementary logic primitives are the majority gate, inverter and wire. In QCA, two different event cell orientations for the realisation of the inverter are available, where the diagonally oriented structure (DOS) is mostly utilised in logic synthesis. However, considering the cell misalignment and displacement, the DOS prevails with a more stable polarised output. But the use of DOS increases cell count which increases the area of the circuit. So, it is desirable to minimise the inverter in a circuit due to the non-availability of the simple logic unit of the inverter. In this paper, two algorithms are proposed for the synthesis of cost-efficient QCA circuits from any boolean function to minimize logic primitives. The proposed role-based mechanism for boolean function synthesis results in the reduction of inverter gate, circuit size, QCA cost and power dissipation. The efficiency of the proposed algorithms has been verified with the realization of standard functions, adders and symmetric functions. A significant improvement in inverter reduction has been reported.

A New Nano-Scale and Energy-Optimized Reversible Digital Circuit Based on Quantum Technology

A nano-scale quantum-dot cellular automaton (QCA) is one of the most promising replacements for CMOS technology. Despite the potential advantages of this technology, QCA circuits are frequently plagued by numerous forms of manufacturing faults (such as a missing cell, extra cell, displacement cell, and rotated cell), making them prone to failure. As a result, in QCA technology, the design of reversible circuits has received much attention. Reversible circuits are resistant to many kinds of faults due to their inherent properties and have the possibility of data reversibility, which is important. Therefore, this research proposes a new reversible gate, followed by a new 3 × 3 reversible gate. The proposed structure does not need rotated cells and only uses one layer, increasing the design’s manufacturability. QCADesigner-E and the Euler method on coherence vector (w/energy) are employed to simulate the proposed structure. The 3 × 3 reversible circuit consists of 21 cells that take up just 0.046 µm2. Compared to the existing QCA-based single-layer reversible circuit, the proposed reversible circuit minimizes cell count, area, and delay. Furthermore, the energy consumption is studied, confirming the optimal energy consumption pattern in the proposed circuit. The proposed reversible 3 × 3 circuit dissipates average energy of 1.36 (eV) and overall energy of 1.49 (eV). Finally, the quantum cost for implementing the reversible circuits indicates a lower value than that of all the other examined circuits.

A New Efficient Nanodesign of Composite Gate Based on Quantum Dot Cellular Automata

The development of nanoscale technologies has come from the downsizing of electronic equipment and the inadequacy of CMOS innovation resulting from hybrid circuit establishment and its failure to respond to nanoscale. Quantum-based technologies, like quantum-dot cellular automata (QCA), are likely to succeed the present technologies due to their incredible benefits, like faster processing, smaller footprints and ultra-low energy usage. In arithmetic and comparison circuits, the fundamental gate is frequently used. Arithmetic logic circuits centered on OR, AND and NOT logic gates have a low design complexity. To obtain complicated logic gates, several architectures have been proposed in the QCA. This work offers a QCA composite gate that achieves all critical digital logic gates, including Inverter, OR, AND, NAND, NOR and exclusive gates like XOR and XNOR. All basic logic is generated in a single unit with this architecture. Only 0.09[Formula: see text][Formula: see text]m2 of area, three three-input majority gates, one XOR, three Inverters, and 0.5 clock zones were required for the suggested circuit. As a result, a decrease of 33% in cell count is achieved compared to the previous systems. The design is evaluated and the dissipated energy is analyzed. For the research on power dissipation, the QCADesigner-E simulator is used to verify the final result. The simulation outcomes show that the suggested layout is advantageous over earlier constructions regarding the area, number of cells, clock phases and cost.

Design and implementation reversible multiplexer using quantum-dot cellular automata approach

Rapid progress in the field of nanotechnology includes using quantum dot-cellular automata (QCA) as a replacement for conventional transistor-based complementary metal oxide semiconductor (CMOS) circuits in the construction of nano-circuits. Due to ultra low thermal dissipation, rapid clocking, and extremely high density, the QCA is a rapidly growing field in the nanotechnological field to inhibit the field effect transistor (FET)-based circuit. This paper discusses and evaluates two multiplexer (MUX) architectures: an innovative and effective 4×1 MUX structure and an 8×1 MUX structures using QCA technology. The suggested architectural designs are constructed using the Fredkin and controlled-NOT (CNOT) gates. These constructions were designed to simulate using tool QCA designer 2.0.3. The 591 and 1,615 cells would be used by the 4×1 and 8×1 QCA MUX architectures, respectively. The simulation results demonstrate that, when compared to the previous QCA MUX structures, the suggested QCA MUX designs have the best clock latency performance and use of different gate types.

Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits

Approximate computing (AC) offers benefits by reducing the requirement for full accuracy, thereby reducing power consumption and area. The majority logic (ML) gate functions as the fundamental logic block of many emerging nanotechnologies. In this article, ML-based arithmetic circuits, i.e., multibit adders and multipliers, are proposed. These adders are designed to prevent the propagation of inexact carry-out signals to higher order computing parts to enhance accuracy. We implemented the proposed multiplier by using a unique partial product reduction (PPR) circuitry, which was based on the parallel approximate 6:3 compressor. Several logic implementation costs, error metrics, and layouts implemented by quantum-dot cellular automata (QCA) are analyzed to evaluate the adder designs. A significant improvement is observed over previous ML-based designs based on the experimental results. The proposed designs are further evaluated using both a neural network (NN) accelerator and image processing. A structural similarity (SSIM) value of 1 and a peak signal-to-noise ratio (PSNR) value of infinity are achieved by the proposed adder design.