Quantum-dot Cellular Automata Structures Research Articles

An ultra-efficient design of fault-tolerant 3-input majority gate (FTMG) with an error probability model based on quantum-dots

Quantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of resistance of QCA circuits under defects in previous works is a vital challenge affecting the stability of the circuit and output production. In addition, with the high defect rate in QCA, suggesting resistance and stable structures is critical. Furthermore, the 3-input majority gate is a fundamental component of QCA circuits; therefore, improving this essential gate would enable the development of fault-tolerant circuits. This paper recommends a 3-input majority gate which is 100% fault-tolerant against single-cell omission defects. Moreover, the fundamental gates are introduced based on the proposed gate. In addition, an adder and a 1:2 decoder are also designed. Using QCADesigner 2.0.3 and QCAPro software, simulations of structures and analysis of power consumption are performed.

Single‐bit digital comparator circuit design using quantum‐dot cellular automata nanotechnology

AbstractThe large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra‐nanoscale region. Circuit designers explore a new technology for the ultra‐nanoscale region, which is the quantum‐dot cellular automata (QCA). Low‐energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low‐complexity, QCA‐based one‐bit digital comparator circuit for the ultra‐nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer‐E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.

Design and analysis of single layer quantum dot-cellular automata based 1- bit comparators

Quantum dot-cellular automata (QCA) technology has recently emerged as a potential candidate for the design of nanometer-scale computational circuits. In digital logic circuits, the comparator is the basic building block for comparing two binary values. This paper presents and implements two 1-bit QCA-based comparator designs. The proposed QCA implementations are compact, require only a single layer and are less complex compared to recently reported designs. The QCADesigner tool has been used to confirm the functional validity of the proposed QCA structures. The simulation results of the proposed comparators have shown considerable improvements compared to their existing counterparts in terms of the number of QCA cells and occupational area requirements in addition to cost and efficient complexity values. Furthermore, all of the proposed structures are dissipating extremely low energy values. Thus, the proposed QCA-based comparators can be viewed as viable options for low power digital applications.

An efficient structure for designing a nano-scale fault-tolerant 2:1 multiplexer based on quantum-dot cellular automata

Quantum-dot Cellular Automata (QCA) is a unique and appealing technique for developing and implementing high-performance and low-power digital circuits at the nanometer scale. In this technology, fault-tolerant circuits guarantee reliability circuits through cells redundancy. Therefore, fault-tolerant and optimized architecture are very important in designing a wide range of QCA circuits. However, although there are some QCA structures for multiplexer designs in the literature, QCA characteristics can be used to design a more optimized multiplexer rather than blindly modeling traditional logic in QCA. As a result, we developed an alternate version of the proposed approaches that leverage fault-tolerant design methodologies. In this article, a new structure for a fault-tolerant 2:1 multiplexer in QCA technology is suggested. Cell redundancy on the wire, NOT gates and majority gates are used. Simulating the suggested designs and demonstrating their correctness was done with QCADesigner 2.0.3. When the additional cell or single missing cell fault occurs in the QCA architecture, the suggested fault-tolerant multiplexer can achieve 90% fault tolerance.

Design and Analysis of Single layer QCA based 1- bit Comparators

Quantum dot-cellular automata (QCA) technology is emerging as a potential candidate for the design of nanometer-scale computational circuits. In digital logic circuits, the comparator is the basic building block for comparing two binary values. This paper presents the design and implementation of two 1-bit QCA based comparators. The proposed QCA implementations are compact, require only a single layer and are therefore less complex compared to recent reported designs. The QCADesigner tool has been used to confirm the functional validity of the proposed QCA structures. The simulation results of the proposed comparators have shown considerable improvement compared to current comparators in terms of cell count, area, cost and efficient complexity. In addition, the proposed 1-bit comparator structures achieved a 25.8 % and 54.5% reduction in the number of cell requirements when compared to the best comparator designs. Moreover, both of the proposed structures achieve low cost and efficient complexity values relative to the recently reported structures. Moreover, all of the proposed structures are dissipating extremely low energy. Thus, proposed QCA based comparators can be viable option for low power digital applications.

A Defects Simulator for Robustness Analysis of QCA Circuits

Although QCA (Quantum-dot Cellular Automata) is a promising nanotechnology to replace CMOS (Complementary Metal-Oxide-Semiconductor), it has several known reliability problems. Consequently, the design of robust QCA structures is a mandatory step towards the consolidation of this new technology. This paper presents a novel methodology for error analysis of QCA structures based on deterministic and random insertion of possible defects to either the cells and to the phase shifts of the clocking circuit. Further features presented are an evaluation of structures robustness and identification of the design elements most susceptible to the defects. Simulation results obtained from the implemented QCA Defects Simulator indicate the feasibility of the proposed error exploration methodology, also revealing starting-points for robustness improvements of known QCA structures.

Design and analysis of efficient QCA reversible adders

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architectures.

Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate

Quantum-dot Cellular Automata (QCA) as a nanoscale transistor-less device technology offers distinguishing advantages over the limitations of CMOS circuits. This nanoelectronic is based on the mapping of binary logic in the two excess electrons configuration within a four-dot cell. In this paper, we propose a new ultra-low energy and low-complexity two-input XOR gate which can be employed as a basic component in designing a wide range of QCA logical circuits. For performance evaluation of the presented design in a large array of QCA structures, even parity generator circuit with different lengths up to 32 bits as well as LFSR circuit are designed and analyzed as instances of logical circuits. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from hardware implementation requirements and energy consumption aspects. QCADesigner tool is utilized to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool.

QCAPUF: QCA-based physically unclonable function as a hardware security primitive

Physically unclonable functions (PUFs) are increasingly used as innovative security primitives to provide the hardware authentication and identification as well as the secret key generation based on unique and random variations in identically fabricated devices. Security and low power have appeared to become two crucial necessities to modern designs. As an emerging nanoelectronic technology, a quantum-dot cellular automata (QCA) can achieve ultra-low power consumption as well as an extremely small area for implementing digital designs. However, there are various classes of permanent defects that can happen during the manufacture of QCA devices. The recent extensive research has been focused on how to eliminate errors in QCA structures resulting from fabrication variances. By a completely different vision, to turn this disadvantage into an advantage, this paper presents a novel QCA-based PUF (QCAPUF) architecture to exploit the unique physical characteristics of fabricated QCA cells in order to produce different hardware fingerprint instances. This architecture is composed of proposed logic and interconnect blocks that have critical vulnerabilities and perform unexpected logical operations. The behaviour of QCAPUF is thoroughly analysed through physical relations and simulations. Results confirm that the proposed QCAPUF has state of the art PUF characteristics in the QCA technology. This paper will serve as a basis for further research into QCA-based hardware security primitives and applications.

A novel configurable flip flop design using inherent capabilities of quantum-dot cellular automata

One of the most attractive fields in quantum-dot cellular automata (QCA) is the implementation of configurable structures. In this paper, a novel QCA structure of a configurable flip-flop (CFF) element is introduced. In a bottom-up design approach, this paper firstly proposes well-organized QCA layouts for a positive/negative clock signal generator, a level/edge pulse converter, and a bit transport/toggle storage block. In the next step, these blocks are connected in a cascade construction to form a robust and efficient flip-flop element with a comprehensive configurable capability. The simulation results demonstrate the accuracy of proposed QCA-based structures. Design capability and flexibility of the proposed CFF element are further evaluated through the synthesis of high-level circuits including registers and counters. Consequently, this new element is the best building block to be used in the next generation of configurable systems such as QCA-based FPGAs.

Element Technology of Quantum-Dot Cellular Automata Based Circuit Design

In this paper, we briefly introduce the element technology for constructing combinational circuits on Quantum-dot Cellular Automata (QCA). There are various combinational circuits including encoder, decoder, adder, subtractor and multiplexer. For the design of the circuits in QCA, there are essential element technology such as wire crossing, inverting structure and majority gate. Thus we simply present the important factor technology to design efficient QCA structures.

Binary to gray and gray to binary converter in quantum-dot cellular automata

The current VLSI technology is based on CMOS technology. The recent challenges of this technology caused to proposed new technology based on quantum-dot cellular automata (QCA). Structures in this technology are based on quantum cells and their sizes are nanoscale. This feature is caused to occur faults in QCA circuits. To resolve this problem can be used testable reversible logic gates in circuits. In this paper, we propose a new two-input XOR gate. Then we describe a non-reversible QCA structure and subsequently reversible QCA structure for 4-bit binary to gray and gray to binary converter. These structures are simulated with QCADesigner and compared with previous structures.

Design and analysis of new fault-tolerant majority gate for quantum-dot cellular automata

Due to its ultrasmall size and extremely low power consumption, quantum-dot cellular automata (QCA) technology represents a promising alternative to semiconductor transistors at the nanoscale. Nevertheless, the design of QCA circuits is limited by their high defect rate during fabrication, making fault-tolerant QCA structures a popular research topic. The aim of this work is to design a new fault-tolerant QCA majority gate based on a $$3\times 5$$3×5 tile. The majority gate guarantees good fault tolerance under single cell and double cell missing defects compared with several previous structures. The functional results when adopting the polarization and kink energy of the proposed majority gate under such single cell and double cell deposition defects are fully investigated. Besides, a series of new fault-tolerant adders are implemented based on the fault-tolerant majority gates. To evaluate the performance of the proposed adders, a thorough comparison versus previous adders with respect to fault tolerance, cell number, area, and delay is carried out. The results indicate that the proposed design can reach a high level of fault tolerance, and perform rather well in terms of other properties. For simulation analysis, the QCADesigner tool is used to check the functionality of all circuits.

A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of $$0.02\,\upmu \hbox {m}^{2}$$0.02μm2 and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.

Towards the design of hybrid QCA tiles targeting high fault tolerance

The increasing fabrication cost of CMOS-based computing devices and the ever-approaching limits of their fabrication have led to the search for feasible options with high device density and low power waste. Quantum-dot cellular automata (QCA) is an emerging technology with such potential to match the design target beyond the limits of state-of-the-art CMOS. But nanotechnologies, like QCA are extremely susceptible to various forms of flaws and variations during fabrication at nano scale. Thus, the exploration of ingenious fault tolerant structure around QCA is gaining high importance. This work targets a new robust QCA tile structure hybridizing rotated and non-rotated cell together resulting lesser kink energy. Different QCA logic primitives (majority/minority logic, fanout tiles, etc.) are made using such hybrid cell structure. The functional characterization using the kink energy and the polarization level of such QCA structures under different cell defects have been thoroughly investigated. The results suggest that the proposed QCA logic primitives have achieved high fault tolerance of 97.43 %. Also, 100 % fault tolerance can be ascertained if the proposed logic circuit drives the correct output with the application of $$\langle $$?001, 011$$\rangle $$? as a primitive test vector only. A comparative performance of the proposed logic over existing structure makes it more reliable.

Realization of Combinational Multiplier using Quantum Cellular Automata

Quantum dot cellular automata(QCA) shows promise as a post silicon CMOS,low power computational technology.Nevertheless,to generalize QCA for next generation digital devices,the ability to implement conventional programmable circuits based on NOR,AND and OR gates is necessary.We devise a new QCA structure,the QCA multiplier,employing the five quantum dot QCA cell.The structure can multiply two 4 bit binary number.Tihis work is motivated by the fact that implementing combinational multiplier using QCA will reduce its area and consequently its heat dissipation.The efficacy of our framework is that it uses QCA majority gates as its primitives.

Matrix Multiplication Using Quantum-Dot Cellular Automata to Implement Conventional Microelectronics

Quantum-dot cellular automata (QCA) shows promise as a post silicon CMOS, low power computational technology. Nevertheless, to generalize QCA for next-generation digital devices, the ability to implement conventional programmable circuits based on NOR, AND, and OR gates is necessary. To this end, we devise a new QCA structure, the QCA matrix multiplier (MM), employing the standard Coulomb blocked, five quantum dot (QD) QCA cell and quasi-adiabatic switching for sequential data latching in the QCA cells. Our structure can multiply two N x M matrices, using one input and one bidirectional input/output data line. The calculation is highly parallelizable, and it is possible to achieve reduced calculation time in exchange for increasing numbers of parallel matrix multiplier units. We show convergent, ab initio simulation results using the Intercellular Hartree Approximation for one, three, and nine matrix multiplier units. The structure can generally implement any programmable logic array (PLA) or any matrix multiplication based operation.