Quantum-dot Cellular Automata Nanotechnology Research Articles

Implementation of EXOR and Subsequent Modular Circuits for Application at Nanoscale Level

Evolving as an outperforming nanotechnology, quantum-dot cellular automata (QCA) is being efficiently used for the design and development of digital modules. This paper presents a novel design for an ultra-efficient exclusive-OR (EXOR) gate in QCA nanotechnology using the cell translation technique. The analysis for fault tolerance and power dissipation of the proposed design is also assessed. To establish the effectiveness of the proposed design, an extensive comparison with the existing designs is provided. As a test bench implementation, the proposed EXOR gate is available as a module for the development of a parity checker, a full subtractor, and a 4-input binary to gray (B2G) code converter in QCA. The cell count for the proposed design of the EXOR gate, full subtractor, parity checker, and 4-input B2G converter is 8, 35, 24, and 24, and the total area (µm2) is 0.0039, 0.0259, 0.01749, and 0.0129, respectively. The proposed EXOR gate design outclasses the hitherto prevailing designs both in terms of the operational parameters and the dissipation of energy. The design simulations have been performed in QCA Designer 2.0.3, and the energy dissipation analysis has been executed in QCA Designer-E and QCAPro.

Novel design of cryptographic architecture of nanorouter using quantum-dot cellular automata nanotechnology

The article introduces a revolutionary Nanorouter structure, which is a crucial component in the Nano communication regime. To complete the connection, many key properties of Nanorouters are investigated and merged. QCA circuits with better speed and reduced power dissipation aid in meeting internet standards. Cryptography based on QCA design methodologies is a novel concept in digital circuit design. Data security in nano-communication is crucial in data transmission and reception; hence, cryptographic approaches are necessary. The data entering the input line is encrypted by an encoder, and then sent to the designated output line, where it is decoded and transferred. The Nanorouter is offered as a data path selector, and the proposed study analyses the cell count of QCA and the circuit delay. In this manuscript, novel designs of (4:1)) Mux and (1:4) Demux designs are utilized to implement the proposed nanorouter design. The proposed (4:1) Mux design requires 3–5% fewer cell counts and 20–25% fewer area, and the propsoed (1:4) Demux designs require 75–80% fewer cell counts and 90–95% fewer area compared to their latest counterparts. The QCAPro utility is used to analyse the power consumption of several components that make up the router. QCADesigner 2.0.3 is used to validate the simulation results and output validity.

A new nano-design of configurable logic module based on coplanar reversible adder and modified Fredkin gates using quantum technology

Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.

Ultra-optimized demultiplexer unit design in quantum-dot cellular automata nanotechnology

Integrated circuit designers face challenges in using complementary metal oxide semiconductor (CMOS) technology as it has a large leakage current and scalability challenge in ultra-nanoscale regime. Quantum-dot Cellular Automata (QCA) is a nanotechnology that can replace CMOS for designing ultra-deep submicron circuits and overcoming CMOS limitations. In this research paper, a novel area-efficient 1:2 demultiplexer is proposed using QCA technology. A demultiplexer is an important combinational circuit used in communication systems and computer memories. It receives serial input data and routes data in parallel to multiple outputs. QCA Designer and QCA Pro-tools are used for layout, simulation, and analysis of power dissipation. 11 QCA cells are utilized in the construction of the proposed 1:2 demultiplexer. The cell area and layout cost of the proposed demultiplexer have improved to 42.11 % and 55.56 % of the current best design, respectively. An essential factor to consider when developing integrated circuits is power dissipation. The proposed design dissipates less power. The energy dissipation of the proposed design has improved to 57.67 % at the kink energy level of 1.5 of the current best design.

Fault-tolerant universal reversible gate design in QCA nanotechnology

Quantum-dot cellular automata (QCA) nanotechnology is the best suited technology for the nanocomputing applications. The limitations of the conventional transistors in nanoscale region can be removed by QCA nanotechnology. Hence, this paper proposes a novel design and implementation of a 3 × 3 universal and reversible gate in QCA nanotechnology. The proposed gate requires only 39 cells and has a total area of 0.029 µm2 with a latency of 0.25. The proposed gate is evaluated for the various possible defects and the performance parameters. The proposed gate is also compared with the existing gates and the proposed gate is established as the most efficient and productive.

Universal and Reversible Gate Design in Quantum-dot Cellular Automata Nanotechnology

Background: Growing progress in the field of nanoelectronics necessitates ever more advanced nanotechnology due to the continued scaling of conventional devices. For the purpose of fabricating current integrated circuits (ICs), Quantum-dot cellular automata (QCA) nanotechnology is the most suitable substitute for complementary metal oxide semiconductor (CMOS) technology. The problem of short-channel secondary effects at the ultra-nanoscale level confronts CMOS technology Aims: QCA nanotechnology overcomes the issues of conventional logic circuit design methods due to its numerous advantages. This research work aims to design an energy-efficient, reliable, universal, 3×3, and reversible logic gate for the implementation of various logical and Boolean functions in QCA nanotechnology. Objective: It is desirable for portable systems to have a small size, extremely low power consumption, and a clock rate in the terahertz. As a result, QCA nanotechnology is an incredible advancement for digital system applications and the design of future systems. Methods: This research article proposes a novel, ultra-efficient, multi-operative, 3×3 universal reversible gate implemented in QCA nanotechnology using precise QCA cell interaction. The proposed gate is used for the implementation of all the basic logic gates to validate its universality. The implementation of all thirteen standard Boolean functions establishes the proposed gate's multi-operational nature. The energy dissipation analysis of the design has been presented for the varying setups. Results: The proposed gate is area-efficient because it uses minimum QCA cells. Various logical and Boolean functions are effectively implemented using the proposed gate. The result analysis establishes the minimum energy dissipation of the proposed design and endorses it as an ultra-efficient design. Conclusion: The QCA cell interaction method demonstrates the best way to design a universal, reversible, and multi-operative gate.

Correction: A novel design of an ultra-low-cost (m × n) multilayer RAM structure in quantum-dot cellular automata nanotechnology

Correction: A novel design of an ultra-low-cost (m × n) multilayer RAM structure in quantum-dot cellular automata nanotechnology

A novel design of an ultra-low-cost (m × n) multilayer RAM structure in quantum-dot cellular automata nanotechnology

A novel design of an ultra-low-cost (m × n) multilayer RAM structure in quantum-dot cellular automata nanotechnology

New Methodology for the Design of Nanostructured Integrated Circuits

Background: A metal oxide semiconductor field effect transistor (MOSFET) is widely used to make integrated circuits (ICs). MOSFET devices are reaching the practical limitations for further scaling in the nanoscale regime. It motivates the researchers to explore and develop new ways to advance the electronics industry. Quantum-dot cellular automata (QCA) is a potential way to replace the MOSFET devices in the nanoscale regime. QCA nanotechnology not only solves the issue of scalability but also degrades the leakage current. It has numerous benefits, such as a highly dense design, fast speed, and energy efficiency compared to complementary metal-oxide-semiconductor (CMOS) technology. Objective: An extensive study of QCA nanotechnology is needed to quickly understand the field. Optimizing the QCA designs is the mandatory requirement to minimize the occupied cell area, latency and quantum cost. The preliminary knowledge of QCA nanotechnology boosts the idea of generating different logic functions. This review paper presents the methodology for making the fundamental logic gates using QCA nanotechnology. XOR gate is commonly used to implement popular circuits such as adders, subtractors, comparators, code converters, reversible gates etc. The various available QCA-based 2-input XOR gate designs are discussed and compared for the different performance metrics. Methods: Columbic interaction causes logical operations, and data is transferred from one cell to another cell using cell-to-cell interaction. A specific arrangement of QCA cells produces a specific logic. QCA Designer tool using a Bi-stable simulation engine is used to design different digital circuits. Results: This review paper deals with the design of the 2-input XOR gate. The considered performance metrics for the comparison purpose are cell count, occupied area, clock cycle, and quantum cost. Existing works on 2-input XOR gates show that a minimum of 8 QCA cells are needed for a 2-input XOR gate using QCA nanotechnology. A single clock cycle-based 2-input XOR gate requires at least 9 QCA cells. The quantum cost can be minimized by reducing the number of QCA cells and clock cycles. Conclusion: This review paper helps the circuit designers to select the appropriate 2-input XOR gate for the design of complex circuits. Circuit designers can use the fundamental concepts detailed in the paper to implement any Boolean function and optimize it for the existing designs. A researcher had developed a 2-input XOR gate using only 8 QCA cells with 0.50 clock cycles. Therefore, designers can start from here to further optimize the 2-input XOR gate with a single clock cycle.

3-bit Shift Register Using QCA Nanotechnology

Background:: Quantum-dot Cellular Automata (QCA) is a new emerging nanotechnology that has been proven to be an improved alternative to complementary metal oxide semiconductor (CMOS) technology. It consists of a group of cells that can perform computational functions when combined and arranged in a particular manner. Objective:: The Flip-Flops are widely affiliated with the circuits of logical and arithmetic unit structures that are used for the processors. Data (D) Flip-Flop is the most important and widely used Flip-Flop among all different types due to its better performance and efficiency. Hence, an efficient D Flip-Flop needs to be developed using QCA nanotechnology. Method:: This paper proposes a new design for D Flip-Flop in QCA nanotechnology. The proposed D Flip-Flop has 28 quantum cells and covers an area of 0.03 μm2 . Furthermore, the paper presents a new design for a 3-bit Shift Register using the proposed D Flip-Flops in QCA nanotechnology keeping in mind the importance of the same in storing and transferring multiple bits of data. Result:: The proposed D Flip-Flop and the 3-bit Shift Register are compared with the existing QCAbased designs. The proposed Shift Register has 100 quantum cells and covers an area of 0.11 μm2 . Conclusion:: The comparison concludes that the proposed D Flip-Flop and the 3-bit Shift Register have used a lesser number of QCA cells and covered smaller areas than the previous works. The proposed designs have been designed in a single layer without any crossover.

QCA-Based Reliable Fundamental Units for Multiplexer-Demultiplexer and D-Flip-Flop

Quantum-dot cellular automata (QCA) is an advanced nanotechnology. It is applied to delineate nanoscale technology-based logic circuits. It can potentially be replaced the complementary metal oxide semiconductor (CMOS) technology. This paper proposes an optimal and single clocked multiplexer (Mux) circuit, which is made with the help of 12 number of QCA cells in QCA nanotechnology. The proposed Mux circuit is designed in such a way that it can be used easily for the design of the demultiplexer (DeMux) and data flip-flop (DFF) circuits. The proposed Mux is easily converted to DeMux by exchanging the input and output terminals only. The effectiveness of the proposed Mux, DeMux, and DFF is examined with the designs that are similar and available in literature using the QCA Designer-E and QCA Pro tools. The design of the proposed Mux is 89.06% fault-tolerant and has decreased the quantum cost by 62.50% as compared to best reported design. Energy measurement plays a key role when designs are operating at nanoscale level. Energy approximation is done with the help of the QCA Pro tool. The proposed designs are more energy efficient compared to the existing works.

A Space-Efficient Universal and Multi-Operative Reversible Gate Design Based on Quantum-Dots

Because of the high speed, low-power consumption, low latency and possible use at the atomic and molecular levels, Quantum-dot Cellular Automata (QCA) technology is one of the future nanoscale technologies that can replace the present transistor-based technology. For the purpose of creating QCA circuits, reversible logic can be regarded as an appropriate candidate. In this research, a new structure for multi-operative reversible designs is suggested. The Saeid Nima Gate (SNG), proposed in this research study, is a brand-new, incredibly effective, multi-operative, universal reversible gate implemented in QCA nanotechnology employing both majority and inverter gates. Reversible gates, also known as reversible logic gates, are gates that have n inputs and n outputs, which is an equal number of inputs and outputs. The amount of energy lost during computations will be reduced if the numbers of inputs and outputs are identical. The proposed gate is modified and reorganized to optimize further, employing exact QCA cell interaction. All fundamental logic gates are implemented using it to demonstrate the universality of the proposed SNG. Reversible logic has advanced, and as a result, our suggested solution has a lower quantum cost than previously reported systems. The suggested design is simulated using the QCADesigner-E tools.

A novel design for managing the faults of the 2 × 2 nano-scale crossbar using quantum-dots

Due to new challenges in transistor technology, non-traditional design approaches and processes have risen to the fore. Quantum-dot Cellular Automata (QCA) nano-technology is a fascinating design method that uses columbic repulsion to transmit and manipulate data. On the other hand, crossbar circuits are critical areas in digital circuits and a signal across several users. A new design is suggested in this paper for a crossbar circuit to manage the faults and decrease the complexity. This paper creates the fault-tolerant crossbar circuit by combining a fault-tolerant majority gate. The clock zone technique is used to implement the suggested architecture. As a result, the suggested design is less susceptible to manufacturing flaws. In addition, the proposed design can manage energy dissipation efficiently. QCADesigner-E is used for simulation and energy dissipation studies. The suggested fault-tolerant crossbar circuit in QCA nano-technology has only 156 cells and 0.18 µm2 area.

Multibit Full Comparator Logic in Quantum-Dot Cellular Automata

In the last few years, binary comparators have received a great deal of attention as parts of complex computational data-paths. However, while several multi-bit architectures have been demonstrated using conventional CMOS technologies, few examples of n-bit comparators, with n higher than 4, can be found in literature for designs based on emerging nanotechnologies, such as the Quantum Dot Cellular Automata, the Nano Magnetic Logic, and many others. This brief proposes a novel approach to design efficient multi-bit binary comparators using the Quantum Dot Cellular Automata nanotechnology. The approach here presented allows improving state-of-the-art competitors in terms of computational complexity and average energy consumption. As an example, in comparison with its direct counterparts, the 32-bit comparator designed as proposed here saves up to 26%, 23% and 11% of the occupied area, the used basic cells and the average energy consumption, respectively. When implemented using the Nano Magnetic Logic, the 4-bit version of the novel comparator uses 1183 magnets and 38 clock phases.

Single layer adder/subtractor using QCA nanotechnology for nanocomputing operations

Quantum-dot cellular automata (QCA) nanotechnology is a suitable replacement for the widely accepted complementary metal oxide semiconductor (CMOS) technology. CMOS technology faces the issues of high-leakage current and non-scalability in the ultra-deep submicron (ultra-DSM) regime. It motivates the researchers to explore new technologies for further advancement of the field. QCA nanotechnology is energy-efficient technology and it overcomes the issues of CMOS technology in ultra-DSM regime. In this paper, a novel 3-input XOR structure is presented using QCA nanotechnology. The full adder and the full subtractor circuits based on the 3-input XOR gate are developed. A circuit for the full adder/subtractor nanostructure is proposed in the paper. All the proposed designs are optimal, fault-tolerant and single-layered. The proposed full adder contains only 21 QCA cells, while 22 QCA cells are required for the proposed full subtractor. The proposed full adder/subtractor structure consists of only 30 QCA cells. The proposed designs are compared with the existing designs for the number of QCA cells, total cell area, total covered area, area utilization, clock latency, QCA layout cost, and crossover requirement. The energy-efficient behaviour of the proposed circuits is calculated using the QCA Designer-E and the QCA Pro tools.

Design, Synthesis and Assessment of QCA primitives of 5-input Majority gate in field-coupled QCA Nanotechnology

Quantum-dot Cellular Automata (QCA) is an exciting new development in the field of nanoscale-based very large scale integration (VLSI) that has the potential to replace more conventional complementary metal oxide semiconductor (CMOS) technology. In this article, a thorough and detailed description of the novel QCA based 5-input Majority gate is presented. In order to validate the accuracy of a 5-input majority gate, a comprehensive analysis has been carried out, taking into account the location of each and every QCA cell inside a structure. In this paper, a completely new 1-bit full-adder is constructed in order to assess the possible advantages offered by the recently developed 5-input majority gate. The comparative analysis with the reported designs in the literature revealed that the proposed full adder is superior in terms of cell count with a reduction of more than 54.79 %, as well as a decrease in area of more than 25 %, and a reduction in latency of 83.33 %. These findings were derived from the observation that the proposed full adder is better. For the purpose of demonstrating the usefulness and dependability of the strategy, power analysis have been carried out on the proposed full adder design using the QCAPro and QCADesigner 2.0.3 tools, respectively. The new majority gate technique is based on a variety of designs that enjoy the parameters of less area, durable circuit architecture, and optimal clock cycles, as well as the higher performance aspects associated with high-speed computation.

Ultra-Low-Cost Design of Ripple Carry Adder to Design Nanoelectronics in QCA Nanotechnology

Due to the development of integrated circuits and the lack of responsiveness to existing technology, researchers are looking for an alternative technology. Quantum-dot cellular automata (QCA) technology is one of the promising alternatives due to its higher switch speed, lower power dissipation, and higher device density. One of the most important and widely used circuits in digital logic calculations is the full adder (FA) circuit, which actually creates the problem of finding its optimal design and increasing performance. In this paper, we designed and implemented two new FA circuits in QCA technology and then implemented ripple carry adder (RCA) circuits. The proposed FAs and RCAs showed excellent performance in terms of QCA evaluation parameters, especially in cost and cost function, compared to the other reported designs. The proposed adders’ approach was 46.43% more efficient than the best-known design, and the reason for this superiority was due to the coplanar form, without crossovers and inverter gates in the designs.

Efficient designs of high-speed combinational circuits and optimal solutions using 45-degree cell orientation in QCA nanotechnology

To fabricate digital logic circuits withsmaller size, ultra-low power consumption, high-speed, and reliable operation at high frequencies like THz. The quantum-dot cellular automata (QCA) are a novel nanoelectronics nano-technology. It is considered a resolution to the scaling problems in CMOS and VLSI technology. This paper will implement nanoscale-based adder, subtractor, and 1-bit comparator structures using QCA nanotechnology. It is being researched as a possible replacement for traditional CMOS technology. In this paper, we have proposed and investigated the cell rotation problem and provided optimal solutions of 45-degree cell arrangement with its appropriate position. The proposed QCA design effectively reduces the cell count and required area inμm2propagation delay and the complexity of the circuits. The proposed simulation-results of a two-input adder, subtractor, and 1-bit comparator architecture were examined and compared with existing designs using the QCADesigner-E tool. The proposed adder, subtractor and 1-bit comparators occupy design area of 21240.00 nm2 (0.02 um2), 21182.00 nm2 (0.02 um2) and 31284.00 nm2 (0.03 um2) respectively. The observed latency is 0.5 clock cycles for adder and sub, and 0.75 clock cycles for 1-bit comparators. In terms of used equal four-dots QCA cell of 21 cells for adder, sub, and 33 cells for 1-bit comparators circuits with applied synchronized QCA clock cycles methodology. The presented design in this paper will be useful for designing and explaining nano-devices for usage in various nanotechnology applications.

Quantum dot cellular automata using a one-bit comparator for QCA gates

Due to power dissipation, area, and reliability characteristics, CMOS technology has been influenced in nanosystems. Quantum DotCellular Automata(QCA) is a research project that studies alternative feasible systems that have similar capabilities. A 1-bit comparator was constructed using QCA nanotechnology. There are no crossovers in these circuits, making them simple to build. With a range of 74.81 to 99.87 percent improvement in performance, the new design is exceptionally efficient in terms of delay time, cell count, area, and the quantum cost. Thus, offered designs are typically found in different digital logics that demand a minimal amount of area and low power consumption. QCA Designer and QCA Designer E Tool are used to develop and simulate the 1-bit comparator circuits suggested here. The results show that the designed QCA 1-bit circuit requires 0.02 μm2 of area and 16 QCA cells. A delay of 0.5 clock is also obtainable. Compared to the other QCA circuits, the design of the QCA Comparator Circuit improves efficiency, cell count, delay, and cost.

A Review of QCA Nanotechnology as an Alternate to CMOS

Background: The human ken and understanding about esoteric phenomenon develops the period from space to the sub-atomic level. The passion to further explore the unexplored domains and dimensions boosts the human advancement in a cyclic way. A significant part of such passion follows in the electronics industry. Moore’s law is reaching the practical limitations because of further scaling of metal oxide semiconductor (MOS) devices. The need of a more dexterous and effective technology approach is demanded. Quantum-dot cellular automata (QCA) is an emerging technology which avoids the physical limitations of the MOS device. QCA is a dynamic computational transistor paradigm that addresses device density, power, operating frequency and interconnection problems. It requires an extensive study to know the fundamentals of logic implementation. Objective: Immense research and experiments due same vigor led to the evolving nanotechnology and a feasible alternative to complementary metal oxide semiconductor (CMOS) technology. A comprehensive study is presented in the paper to enhance the basics of QCA technology and the way of implementation of the logic circuits. Different existing circuits using QCA technology are discussed and compared for different parameters. Methods: Scaling the devices can reduce the power consumption of the MOS device. Quantum dots are nanostructures made from semi-conductive conventional materials. It is possible to model these constructions as 3-dimensional (3D) quantum energy wells. Logical operations and data movement are performed using Columbic interaction between nearby QCA cells instead of current flow. Results: The focus of this review paper is to study the trends which have been proposed and compared the designs for various digital circuits. The performance of different circuits such as XOR, adder, reversible gates and flip-flops are provided. Different logic circuits are compared on the parameters such as cell count, area and latency. At least 10 QCA cells are used for the XOR gate with 1 clock latency. Minimum 44 QCA cells are required to make a full adder with 1.25 clock latency. Conclusion: Designer may choose the best fitted circuit in their logic implementation on the basis of the comparison. The comprehensive study of the QCA technology helps the researchers to learn this field fast and work for the design of less cells count and latency.