Quantum-dot Cellular Automata Implementation Research Articles

Mixed-valence realizations of quantum dot cellular automata

This article reviews recent progress in the design and theoretical investigation of molecular implementations of quantum-dot cellular automata (QCA) for field-coupled nanocomputing applications. QCA is a classical computing paradigm based on Coulombic quantum interactions between nanoscale subunits consisting of two or more quantum dots. Shrinking these dots to the molecular scale maximizes device density and permits operation at ambient temperatures. The essential feature of molecular QCA systems is the presence of two or more coupled redox centers separated by spacers. In this work candidate systems ranging from simple organic molecules to self-assembled multi-center mixed-valence organometallic complexes are surveyed, and some of the challenges remaining to be faced both in theoretical understanding and practical implementation are discussed.

Design of Efficient AI Accelerator Building Blocks in Quantum-Dot Cellular Automata (QCA)

Digital circuit design technologies based on Quantum-Dot Cellular Automata (QCA) have many advantages over CMOS, such as higher intrinsic switching speed up to Terahertz, lower power consumption, smaller circuit footprint, and higher throughput due to compatibility of the inherent signal propagation scheme with pipelining. Hence, QCA is a perfect candidate to provide a circuit design framework for applications such as Artificial Intelligence (AI) accelerators, where real-time energy-efficient performance needs to be delivered at low cost. A novel QCA design approach based on optimal mix of Majority and NAND-NOR-INVERTER (NNI) gates with USE (Universal, Scalable, Efficient) clocking scheme, has been investigated in this work for latency and energy consumption improvements to fundamental building blocks in AI-accelerators, including multipliers, adders, accumulators and SRAMs. The common <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 4$ </tex-math></inline-formula> Vedic multiplier has been redesigned using the proposed approach, and simulated to yield 62.8% reduction in cell count, 82.2% reduction in area, and 71.2% reduction in latency. 83% reduction in cell count, 94.5% reduction in area, and 94.6% reduction in latency was simulated for the proposed 8-bit PIPO register. The proposed SRAM cell design is estimated to have similar improvement figures to those achieved by the sub-blocks, such as the D-Latch, which has been simulated to exhibit 44.4% reduction in cell count, 50% reduction in both area and latency, and 73% reduction in energy dissipation. The contributions from this work can be directly applied to low cost, high throughput, energy efficient AI-accelerators that can potentially deliver orders of magnitude better energy-delay characteristics than their CMOS counterparts, and significantly better energy-delay characteristics than state-of-the-art QCA implementations.

Design of SSG‐1 gate‐based cost‐efficient reversible digital circuits using quantum‐dot cellular automata technology

AbstractIn recent times, logic circuit designing with quantum‐dot cellular automata (QCA) technology is being comprehensively researched because of its inherent miniature size, ultra‐high speed, low power dissipation, and better switching frequency in the nanoregime. In this paper, QCA implementation of a 3 × 3 SSG‐1 reversible gate is first proposed. This gate is then used to design a reversible full adder, reversible 1‐bit comparator, and reversible 4:2 compressor. To evaluate the performance of the proposed QCA designs, an in‐depth comparison with existing designs has been performed. It is seen that the proposed SSG‐1 gate is efficient from the existing designs which eventually leads to efficient designs of adders, comparator, and compressor digital circuits. To further validate this, these digital circuits have also been compared with the literature and performance improvement is clearly observed in these circuits. In addition to this, energy dissipation analysis of all proposed logic gates and digital circuits is also performed for different kink energy levels using the QCA Pro tool and their respective energy dissipation maps are also obtained. Based on this, it is seen that the proposed designs are cost‐efficient and dissipate less energy which makes them more appropriate for designing higher‐order lower power circuits.

Design and analysis of single layer quantum dot-cellular automata based 1- bit comparators

Quantum dot-cellular automata (QCA) technology has recently emerged as a potential candidate for the design of nanometer-scale computational circuits. In digital logic circuits, the comparator is the basic building block for comparing two binary values. This paper presents and implements two 1-bit QCA-based comparator designs. The proposed QCA implementations are compact, require only a single layer and are less complex compared to recently reported designs. The QCADesigner tool has been used to confirm the functional validity of the proposed QCA structures. The simulation results of the proposed comparators have shown considerable improvements compared to their existing counterparts in terms of the number of QCA cells and occupational area requirements in addition to cost and efficient complexity values. Furthermore, all of the proposed structures are dissipating extremely low energy values. Thus, the proposed QCA-based comparators can be viewed as viable options for low power digital applications.

Robust Electric-Field Input Circuits for Clocked Molecular Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is a paradigm for low-power, general-purpose, classical computing designed to overcome the challenges facing CMOS in the extreme limits of scaling. A molecular implementation of QCA offers nanometer-scale devices with device densities and operating speeds which may surpass CMOS device densities and speeds by several orders of magnitude, all at room temperature. Here, a proposal for electric field bit write-in to molecular QCA circuits is extended to QCA circuits clocked using the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$z$</tex-math></inline-formula> component of an applied electric field. Input electrodes, which may be much larger than the cells themselves, apply an input <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$y$</tex-math></inline-formula> field component. The input field selects an input bit on a field-sensitive portion of the circuit, and a shift register transmits the input bit to downstream logic. The circuit is sensitive to the input field, since even a very weak input field selects a bit and drives the shift register as desired. The circuit also is robust: the coupling between the field-sensitive segment and the shift register fails at input field strengths much stronger than those needed to write a bit. A simple rotation of the the shift register cells eliminates this circuit failure, even under arbitrarily strong input fields. The modified circuit also tolerates a significant unwanted <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$x$</tex-math></inline-formula> field component, which is used neither for clocking nor for input. The write-in of classical bits to molecular QCA circuits is one road-block that must be cleared in order to realize energy-efficient molecular computation using QCA. Write-in may be achieved simply by using relatively large electrodes and clocked molecular circuits that respond to a weak input field and tolerate very strong applied fields without failing.

Design and Analysis of Single layer QCA based 1- bit Comparators

Quantum dot-cellular automata (QCA) technology is emerging as a potential candidate for the design of nanometer-scale computational circuits. In digital logic circuits, the comparator is the basic building block for comparing two binary values. This paper presents the design and implementation of two 1-bit QCA based comparators. The proposed QCA implementations are compact, require only a single layer and are therefore less complex compared to recent reported designs. The QCADesigner tool has been used to confirm the functional validity of the proposed QCA structures. The simulation results of the proposed comparators have shown considerable improvement compared to current comparators in terms of cell count, area, cost and efficient complexity. In addition, the proposed 1-bit comparator structures achieved a 25.8 % and 54.5% reduction in the number of cell requirements when compared to the best comparator designs. Moreover, both of the proposed structures achieve low cost and efficient complexity values relative to the recently reported structures. Moreover, all of the proposed structures are dissipating extremely low energy. Thus, proposed QCA based comparators can be viable option for low power digital applications.

Improved QCA-Based Full Adder/Subtractor Structures

Recently, Quantum-dot Cellular Automata (QCA) technology has shown great potential over current CMOS technology as it offers energy and area- efficient digital nano-scale circuits. In this article, various full adder/subtractor QCA implementations are presented and compared with recently published designs. The proposed designs include dedicated full adder and subtractor structures, combined full adder/subtractor structure and single- layer and multi-layer-controlled adder/subtractor structures. The proposed designs are simulated and evaluated using specialized QCA design tools. It was found that the proposed dedicated full adder and subtractor structures outperform their recently presented counterparts in terms of cell count, area, latency and cost values. In addition, the combined structure has achieved significant improvements as compared with existing designs. The improvements in cell count, area, latency and cost values have reached up to 82, 86, 66 and 98%, respectively. As compared with the best recent single-layer and multi-layer designs, the proposed single-layer controlled full adder/subtractor structure has achieved up to 46, 55 and 55% improvement in QCA cell count, area and cost value, respectively. On the other hand, the achieved improvement of the proposed multi-layer-based structure has reached up to 29, 43 and 15% in cell count, area and cost value, respectively. Furthermore, it has been observed that the proposed combined/controlled structures are more energy-efficient than the dedicated designs which aligns with the nanoscale circuit design requirements. Finally, the proposed QCA-based structures can be viewed as key building blocks for implementing larger logic designs such as Arithmetic and Logic Units (ALUs).

Low-Energy Eigenspectrum Decomposition (LEED) of Quantum-Dot Cellular Automata Networks

The design and understanding of quantum-dot cellular automata (QCA) networks has been largely influenced by limitations in the approximation methods used in common design tools. In some cases, such limitations have led to unrealistic selections of clock zones which are not feasible for nanoscale QCA implementations given current fabrication constraints on clocking electrodes. A better understanding of the behaviour of larger QCA networks of perhaps tens to hundreds of QCA devices is needed. One approach is by investigating the low energy spectrum; however, diagonalization of the system Hamiltonian even in the 2-state approximation is impractical beyond 20 or so devices. In this work, we present a methodology for understanding the spectrum of the full network in terms of contributions from components of the network. We show that important features of the low energy spectrum can be attributed to specific critical components, and present one scheme for decomposing the network into these components. In addition, we address the question of computing the low energy spectrum of large QCA networks. A method based on basis reduction which naturally emerges from the component decomposition is successfully applied to a 49 cell XOR gate with results compared against a density matrix renormalization group implementation.

In memory computation using quantum‐dot cellular automata

The conventional computing system has been facing enormous pressure to cope with the uprising demand for computing speed in today's world. In search of high-speed computing in the nano-scale era, it becomes the utmost necessity to explore a viable alternative to overcome the challenges of the physical limit of complementary-metal-oxide-semiconductor (CMOS). Towards that direction, the processing-in-memory (PIM) is advancing its importance as it keeps the computation as adjacent as possible to memory. It promises to outperform the latencies of the conventional stored-program concept by embedding storage and data computation in a single unit. On the other hand, the bit storing and processing capability of Akers array provides the foundation of PIM. Again, quantum-dot cellular automata (QCA) emerges as a promising nanoelectronic to put back CMOS to give fast-paced devices at the nanoelectronics era. This work presents a novel PIM concept, embedding Akers array in QCA to achieve high-speed computing at the nano-scale era. QCA implementation of universal logic utilizing Akers array signifies its processing power and puts forth its potentials. A universal function is considered for testing the effectiveness of the proposed PIM cell. The performance evaluation indicates the efficacy of QCA PIM over the conventional Von Neumann architecture.

Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates

Quantum-dot cellular automata (QCA) is one of the promising technologies that enable nanoscale circuit design with high performance and low-power consumption features. As memory cell and flip-flops are rudimentary for most of the digital circuits, having a high speed, and a less complex memory cell is significantly important. This paper presents novel architecture of D flip-flops and memory cell using a recently proposed five-input majority gate in QCA technology and simulated by QCADesigner tool version 2.0.3. The simulation results show that the proposed D flip-flops and the memory cell are more superior to the existing designs by considering the common design parameters. The proposed RAM cell spreads over an area of 0.12[Formula: see text][Formula: see text]m2and delay of 1.5 clock cycles. The proposed level-triggered, positive/negative edge-triggered, and dual edge-triggered D flip-flop uses 14%, 33%, and 21% less area, whereas the latency is 40%, 27%, and 25% less when compared to the previous best design. In addition, all the proposed designs are implemented in a single layer QCA and do not require any single or multilayer wire crossing.

New efficient designs of reversible logic gates and circuits in the QCA technology

Quantum-dot cellular automata (QCA) is a developing nanotechnology, which seems to be a good candidate to replace the conventional complementary metal-oxide-semiconductor (CMOS) technology. The QCA has the advantages of very low power dissipation, faster switching speed, and extremely low circuit area, which can be used in designing nanoscale reversible circuits. In this paper, the new efficient QCA implementations of the basic reversible Gates such as: CNOT, Toffoli, Feynman, Double Feynman, Fredkin, Peres, MCL, and R Gates are presented based on the straight interactions between the QCA cells. Also, the designs of 4-Bit reversible parity checker and 3-bit reversible binary to Grey converter are introduced using these optimized reversible Gates. The proposed layouts are designed and simulated using QCADesigner software. In comparison with previous QCA designs, the proposed layouts are implemented with the minimum area, minimum number of cells, and minimum delay without any wire-crossing techniques. Also, in comparison with the CMOS technology, the proposed layouts are more efficient in terms of the area and power. Therefore, our designs can be used to realize quantum computation in ultralow power computer communication.

Clock Topologies for Molecular Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is a low-power, non-von-Neumann, general-purpose paradigm for classical computing using transistor-free logic. Here, classical bits are encoded on the charge configuration of individual computing primitives known as “cells.” A cell is a system of quantum dots with a few mobile charges. Device switching occurs through quantum mechanical inter-dot charge tunneling, and devices are interconnected via the electrostatic field. QCA devices are implemented using arrays of QCA cells. A molecular implementation of QCA may support THz-scale clocking or better at room temperature. Molecular QCA may be clocked using an applied electric field, known as a clocking field. A time-varying clocking field may be established using an array of conductors. The clocking field determines the flow of data and calculations. Various arrangements of clocking conductors are laid out, and the resulting electric field is simulated. It is shown that that control of molecular QCA can enable feedback loops, memories, planar circuit crossings, and versatile circuit grids that support feedback and memory, as well as data flow in any of the ordinal grid directions. Logic, interconnect and memory now become indistinguishable, and the von Neumann bottleneck is avoided.

Towards modular binary to gray converter design using LTEx module of quantum-dot cellular automata

A modular approach to realize the ultra-fast quantum-dot cellular automata (QCA) generic binary to gray converter is presented in this paper. The novel designs here validated fully exploit the intrinsic repetitive capabilities of the Layered T Exclusive OR (LTEx) module in the QCA domain. An efficient logic formulation of QCA design metrics like O-Cost and delay is proposed for the n-bit QCA binary to gray converter designs. The QCA implementation of n-bit LTEx binary to gray converter is compared with the conventional converters. An attempt has been made to enhance the speed of modular binary to gray converter designs. The proposed 4, 8, 16, 32, 64-bit binary to gray converters need 4.35, 15.88, 15.96, 15.7, 16.68% less O-cost and 11.57, 2.61, 9.32, 12.64, 29.25% less effective area, respectively. Thus the proposed layouts offer the smaller feature size, reduced circuit complexity exploiting the modular based design approach. The simulation results have been carried out in the renowned computer aided design tool, namely QCADesigner 2.0.3 with gallium arsenide heterostructure based parameter environment.

Toffoli Netlist and QCA implementations for existing four variable reversible gates: a comparative analysis

With CMOS reaching its fundamental physical heat threshold limits, reversible logic has emerged as a viable alternative due to its heat arresting attributes. CMOS started witnessing frequency issues with maximum clocking achieved in GHz. Quantum-Dot Cellular Automata (QCA) has already promised THz clocking speeds although in the nascent form. These two domains have set the stage for information lossless substitution of CMOS in near future. QCA implementation provides a realizable implementation of the theoretical reversibility concept. Till date several four variable application specific reversible gates have been proposed but they lack relevant quantum mapping using QCA. This paper proposes both the implementations—Toffoli Netlist designs for the gates using positive control lines (optimized designs using negative control lines wherever possible) and implementations using Quantum-Dot Cellular Automata. The relevant quantum metrics have also been provided for the respective implementations. We also provide the complexity analysis of the four variable reversible gates based on Hamming Distance. This paper is intended to serve as a benchmark for optimized gate choice from among the existing four variable reversible gates for complex Boolean realizations.

Electric-Field Inputs for Molecular Quantum-Dot Cellular Automata Circuits

Quantum-dot cellular automata (QCA) is a low-power, non-von-Neumann, general-purpose paradigm for classical computing using transistor-free logic. An elementary QCA device called a "cell" is made from a system of coupled quantum dots with a few mobile charges. The cell's charge configuration encodes a bit, and quantum charge tunneling within a cell enables device switching. Arrays of cells networked locally via the electrostatic field form QCA circuits, which mix logic, memory and interconnect. A molecular QCA implementation promises ultra-high device densities, high switching speeds, and room-temperature operation. We propose a novel approach to the technical challenge of transducing bits from larger conventional devices to nanoscale QCA molecules. This signal transduction begins with lithographically-formed electrodes placed on the device plane. A voltage applied across these electrodes establishes an in-plane electric field, which selects a bit packet on a large QCA input circuit. A typical QCA binary wire may be used to transmit a smaller bit packet of a size more suitable for processing from this input to other QCA circuitry. In contrast to previous concepts for bit inputs to molecular QCA, this approach requires neither special QCA cells with fixed states nor nanoelectrodes which establish fields with single-electron specificity. A brief overview of the QCA paradigm is given. Proof-of-principle simulation results are shown, demonstrating the input concept in circuits made from two-dot QCA cells. Importantly, this concept for bit inputs to molecular QCA may enable solutions to or provide insights into other challenges to the realization of molecular QCA, such as the demonstration of molecular device switching, the read-out of molecular QCA states, and the layout of molecular QCA circuits.

QCA BASED SECURE NANOCOMMUNICATION BLOCK CIPHER DESIGN BASED ON ELECTRONIC CODE BOOK

In nanotechnology, Quantum Dot-Cellular Automata (QCA) is a new paradigm that can serve as an alternative to CMOS circuits. In comparison to CMOS, QCA has lower device area and faster processing power with an overall low energy consumption. The complexity of cryptographic architecture is a key issue in terms of circuit density and power dissipation.Moreover, security is the major issue in nanocommunication systems. Those issues can be overcome through QCA technology. To date, only few applications of QCA have been explored in the field of cryptography. This paper illustrates the QCA design and implementation of block cipher based on electronic code book (ECB). An encoder circuit, which can function as decoder for ECB is proposed. The design requires only 0.095 I¼m2 area and a latency value of 0.75. The circuit dissipates very low energy which is established through calculation of power dissipation. Due to inherent characteristics, side channel attacks like power analysis attack can be prohibited using proposed circuit. The circuit is implemented on QCA Designer platform and the design accuracy is verified via simulation results.

A novel true random number generator based on QCA nanocomputing

True random number generators (TRNGs) are considered as an innovative basis to obtain unpredictable and irreproducible digital bit-streams in secure systems and communications. Because of its ultra-low power and extremely-small size features, the quantum-dot cellular automata (QCA) is most promising nanoelectronic technology for implementing digital systems with security capabilities. This paper presents a novel QCA implementation of TRNG, which is comprised of proposed cross-coupled circuit and cross-oriented structure, in order to generate truly random numbers. This implementation extracts the randomness from the oscillatory trajectory of QCA cross-coupled loop that is composed of XNOR gates only to guarantee the quality of randomness. Furthermore, it exploits the oscillatory metastability resulting from zero-energy QCA cells of cross-oriented structure that is connected across cross-coupled outputs to increase the quality of randomness. Its behavior is verified through QCA simulations and its architecture is passed statistical tests of random numbers. Consequently, the proposed QCA-based TRNG can be considered as a promising candidate for future security applications in Nano communications.

Efficient Design of Reversible Logic ALU Using Coplanar Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) based reversible logic is the utmost necessity to achieve an architecture at nano-scale, which promises extremely low power consumption with high device density and faster computation. This paper emphasises on the design of an efficient reversible Arithmetic Logical Unit (ALU) block in QCA technology. We have considered [Formula: see text] RUG (Reversible Universal Gate) as the basic unit, and also report a HDLQ model for RUG with 52.2% fault tolerance capability. Further, the reversible ALU has synthesized with reversible logic unit (RLU) and reversible arithmetic unit (RAU). We also demonstrate QCA implementation of RLU and RAU with lesser complexity and cell counts. The proposed ALU needs only 64 MVs (Majority Voters), which demonstrates 40% optimizations in the majority gate counts than the existing result. QCADesigner-2.0.3 is used to verify the proposed designs.

Design of Divider Using Taylor Series in QCA

Quantum-dot cellular automata (QCA) is the promising applicant in nanotechnology for next generation computers. QCA is a very low power, very high speed and extremely dense technology that is used for implementing any computer architecture scrambles binary logics over the configuration of charges amid quantum dots. Numerous studies about multiplier and adder have been anticipated in QCA, while QCA divider design and implementation is a less explored area. Since divider is the basic component of the arithmetic logic unit, thus it has a great impact on the performance of central processing unit (CPU). The widely used algorithms in divider are restoring, non-restoring some of them also used the Goldschmidt iterative division algorithm in QCA, but there is no work reported which has the implementation of the divider based on Taylor series algorithms. We have presented the divider based on a Taylor series expansion algorithm in QCA. The divider has the advantage of time -saving compared to existing dividers.

Jahn-Teller effect in molecular electronics: quantum cellular automata

The article summarizes the main results of application of the theory of the Jahn-Teller (JT) and pseudo JT effects to the description of molecular quantum dot cellular automata (QCA), a new paradigm of quantum computing. The following issues are discussed: 1) QCA as a new paradigm of quantum computing, principles and advantages; 2) molecular implementation of QCA; 3) role of the JT effect in charge trapping, encoding of binary information in the quantum cell and non-linear cell-cell response; 4) spin-switching in molecular QCA based on mixed-valence cell; 5) intervalence optical absorption in tetrameric molecular mixed-valence cell through the symmetry assisted approach to the multimode/multilevel JT and pseudo JT problems.