Quantum-dot Cellular Automata Framework Research Articles

An Efficient Design of a Three-Layer Magnitude Comparator for Nano-Scale IoT Applications Based on QCA Technology

The difficulty of further downscaling CMOS technology arises from the restriction of feature size reduction. Quantum-dot cellular automata (QCA) emerges as a paradigm-shifting successor to CMOS, heralding a new era of effective digital design at the nanoscale. It stands as an enticing frontier in nanoscale computing, with limited exploration into the realms of smaller QCA cells, elevated processing speeds, and more compact area requirements across diverse circuits. Within the intricate landscape of decoding circuits and process controllers, the binary comparator assumes a role of paramount significance. On the other hand, the quickly developing Internet of Things (IoT) market aims to produce high-speed, low-power gadgets. A comparator is a crucial component in the analog-to-digital conversion process used by IoT devices. In order to meet the power and latency requirements of IoT devices, a high-speed, low-power comparator is greatly required. Consequently, the strategic design of comparators within the QCA framework has ascended to a position of heightened importance in cutting-edge research. This study undertakes the formidable task of conceiving QCA-centric designs for MV32, the majority gate, and the inverter gate, thereby contributing to the development of a sophisticated multi-layered comparator architecture for IoT devices. In the realization of a three-layer comparator implemented in QCA, we attain an impressive feat—a minimal clock zone demanding only a singular clock pulse coupled with exceptional compaction (measuring at a mere 0.03 μm2). Experimental revelations corroborate the substantial advancement of the proposed design over traditional methodologies, particularly in terms of circuit area, cell count, and clock efficiency.

A quantum-based building block for designing a nanoscale full adder circuit with power analysis

Quantum-dot cellular automata (QCA) concentrates charges using the Coulomb interaction. Despite the nanometric scale and the extremely high projected working frequency, the need for transmission is eliminated, resulting in very low power consumption. Few designs exist to reduce energy consumption and provide simple access to inputs and outputs. There have been few studies on the optimizations of majority and inverter gates for different types of adders. The design of adders using a QCA framework is becoming more significant in current research. This work aims to design a multi-layered full adder architecture that uses three-input XOR and a majority gate for the QCA framework. The primary goal of this article is to design a circuit with low power consumption and easy access to inputs and outputs. For a full adder by the QCA technology, a minimum clock zone of two clocks and 18 QCA cells by high compaction (0.02 μm2) are obtained. Additionally, the synthesis of high-level logic establishes the design's utility. In comparison to traditional design methodologies, experimental results show considerable design level gains in terms of circuit area, cell count, power, and clock. Experiments show how the design level has significantly improved compared to traditional design methodologies regarding circuit area, cell count, power, and clock.

Cost-effective Programmable Logic Arrays Using Multilayer Structures of Decoders in QCA Framework

The emerging nanotechnology paradigm, Quantum Dot Cellular Automata (QCA) in particular, is gaining a wide recognition due to its high speed, nano feature size and considerably low power consumption. The QCA architecture not only provide potential alternative for Complementary Metal Oxide Semiconductor (CMOS) circuits but its multilayer topology facilitates an added benefit of cost efficacy and immunity towards random interference. Moreover, design of programmable logic devices in QCA is vital to promote the multi-utility and resiliency of the computing circuits. This paper presents the multilayer designs of 2×4 and 3×8 decoder circuits in QCA framework with 55.1% and 51.17% better cost efficiency respectively, over the earlier reported designs. The presented 3×8 decoder circuit is further utilized to implement Programmable Logic Array (PLA) to realize Boolean functions of adder and subtractor. The presented circuits are cost effective and showcase the significance of programmable devices in nano-computing.

Energy Efficient Configurable Layout of Logic Block in QCA Frame Work for an FPGA

Aims: Embedded system plays a vital role in today’s life. Hence, our interest is in areadelay- energy efficient embedded system design in post-CMOS technology, i.e., QCA. Objectives: The research is focused on efficient area-delay-energy Configurable Logic Block (CLB) design for Field-Programmable Gate Array architecture (FPGA) with successful simulation-based on next-generation technology, Quantum-dot cellular automata. Methods: Each proposed circuit is designed on post CMOS 4 dot 2 electron technology, i.e. QCA (Quantum dot Cellular Automata), is adopted in circuit implementation due to low power dissipation, high clock frequency and high package density. QCADesigner is used to verify the functionality of every circuit. QCAPro tool is used for determining power dissipation. Results: In contrast, a new approach of using de-multiplexer replacing the decoder has been introduced that results in the reduction of the average energy dissipation by almost 57%. A NOR based D flip-flop memory architecture and multiplexer are also used in the lookup table for the configurable logic block. The proposed architecture thus reduces the overall latency. The proposed CLB consists of 6356 QCA cells covering 7.44 um2 area. Write and read latency of proposed CLB are 12 and 7.25 QCA clock, respectively. Conclusion: The present paper concludes that read and write latency reduction occurs; average energy dissipation, leakage, and switching energy dissipation are reduced in a large amount resulting in an advantage of the overall minimization of the latency for the proposed CLB in the process.

Power analysis attack resistable hardware cryptographical circuit design using reversible logic gate in quantum cellular automata

Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power exploitation to realize the reversible logic circuit in the nanoscale era. Reversible logic is an alternative to overcome excess energy indulgence of irreversible process. This paper illustrates a cost-effective, energy-efficient Universal Reversible Logic Gate in QCA framework which is capable of designing power analysis attack resistable hardware cryptographical circuit. The proposed (URLGs: U1 and U2) has been tested with simulator QCADesigner V2.0.3, outshined the existing pattern relating to the area, gate count, garbage count, and quantum cost. We found 37.5% garbage minimization is achieved compared to NFT, which is utmost minimization of garbage ever reported in QCA literature. Thirteen three variable standard Boolean functions are considered as logic benchmarks to guesstimate the capability and efficiency of proposed URLG in QCA circuit implementation and synthesizing logic gates. In average, our proposed U2 achieved 36.66% improvement in energy dissipation for different kink energy ratios over early reported work.

Novel True Random Number Generator Based Hardware Cryptographic Architecture Using Quantum-Dot Cellular Automata

Information processing and conventional computing are usually resource constrained; evermore they need to operate in a physically suspicious environment. Consequently, communication architectures, protocol and its security aspects have been the focus of many recent research works. Our proposal demonstrates how to amend this vulnerable circumstance through a three-stage security scheme in quantum-dot cellular automata (QCA) based nano-architecture. The primary objective of this hardware-based cryptographic architecture using QCA is to intend a distinctly secure communication architecture comprising less number of QCA cells, which enchant the comparative performance investigation along with the power-area constraints. In our proposed design the random bits are extorted from an asymmetrically arranged crossed loop TRNG where the seed circuits are used to boost the volatility of initiated number sequences as well as the distinction of the random numbers. In this work, a novel encryption-decryption prototype for a secure communication system has been implemented. The simulation results are obtained from QCADesigner tool v2.0.3, which fruitfully agreed with the industry standard. An intact evaluation of the proposed TRNG and the comparative analysis with a recent work of TRNG has been authorized by the 7.79% improvements in average energy dissipation for different Kink energy ratio. Altogether the proposed architecture and its contemporary implementation in QCA framework can be recognized by means of the advantages in 7.02% circuit complexity, 11.53% area, and 13.77% average leakage power dissipation with respect to the recent work of TRNG. Thus our proposed novel TRNG based hardware cryptographic architecture can be considered as a potential next-generation network-on-chip (NoC) realization for a large-scale cryptosystem in QCA technology.

Study and Performance Analysis of MOS Technology and Nanocomputing QCA

One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.

Low Area Complexity Demultiplexer Based on Multilayer Quantum-dot Cellular Automata

Nanoscience and nanotechnology involve the ability to see and to control individual atoms and molecules. A quantum-dot cellular automata(QCA) is one of the attractive alternative technology among nanotechnology solutions. Demultiplexer is used in communication systems to convert the serial data to the parallel data. A demultiplexer receives the output signals from the multiplexer. For that reason, it is important components for making integrated circuit. This work target is designing a high optimized demultiplexer in QCA framework. We proposed designs of 1:2 and 1:4 demultiplexer and the simulation results reveal that our proposed designs have significant improvements, such as low complexity and power consumption aspects.

Towards the hierarchical design of multilayer QCA logic circuit

As a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises efficient digital design with high device density and low power dissipation in the future. This work targets the development of multi-layered architecture in the QCA framework with the goal to build an efficient methodology for QCA based digital logic design. A strategy for modelling, digital devices around QCA multiplexer is framed, which directs to the conception of complex digital circuits with high device density and low latency (i.e., more quick functioning). The proposed multilayer design also points to inherent aspects of radius of effect of QCA cells and the layer spacing in multilayer architecture. Minimum clock zone (2 clock) with high compaction (0.01μm2) is achieved for the multiplexer designed in QCA framework. A heuristic approach to synthesize multilayer synchronized QCA logic circuit is also proposed. Experimental results illustrate significant improvements in design level in terms of circuit area, cell count and clock over that of conventional design approaches.

Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder

Quantum-dot cellular automata (QCA) has been studied extensively as a promising switching technology at nanoscale level. Despite several potential advantages of QCA-based designs over conventional CMOS logic, some deposition defects are probable to occur in QCA-based systems which have necessitated fault-tolerant structures. Whereas binary adders are among the most frequently-used components in digital systems, this work targets designing a highly-optimized robust full adder in a QCA framework. Results demonstrate the superiority of the proposed full adder in terms of latency, complexity and area with respect to previous full adder designs. Further, the functionality and the defect tolerance of the proposed full adder in the presence of QCA deposition faults are studied. The functionality and correctness of our design is confirmed using high-level synthesis, which is followed by delineating its normal and faulty behavior using a Probabilistic Transfer Matrix (PTM) method. The related waveforms which verify the robustness of the proposed designs are discussed via generation using the QCADesigner simulation tool.

Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU

Reversible logic is emerging as a prospective logic design style for implementing ultra-low-power VLSI circuits. It promises low-power consuming circuits by nullifying the energy dissipation in irreversible logic. On the other hand, as a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises energy efficient digital design with high device density and high computing speed. The integration of reversible logic in QCA circuit is expected to be effective in addressing the issue of energy dissipation at nano scale regime. This work targets the design of reversible ALU (arithmetic logic unit) in QCA framework and proposes a new “Reversible QCA” (RQCA). The primary design focus is on optimizing the number of reversible gates, quantum cost and the garbage outputs that are the most important hindrances in realizing reversible logic. Besides optimization, the fault coverage capability of RQCA under missing/additional cell deposition defects is analysed. The scope of reversible logic is further outstretched by introducing a novel DFT (design for testability) architecture around the reversible ALU that reduces testing overhead. The performance of proposed ALU is evaluated, subjected to different faults, and is established to be more effective than the existing ALU.

Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA

Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.

Design of Efficient Full Adder in Quantum‐Dot Cellular Automata

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

Scalable minority gate: a new device in two-dot molecular quantum-dot cellular automata

Design for scalability is one of the paramount aspects of nanotechnology. The authors present a new architecture for scalable gates in two-dot molecular quantum-dot cellular automata paradigm. Quantum chemical calculations are performed on multiple molecules that are arranged to carry out logic operations at the nanoscale. Compared to previous multi-input gates in four-dot quantum-dot cellular automata framework, the number of used redox centres has been significantly reduced in the presented gates.