Quantum-dot Cellular Automata Design Research Articles

Efficient design of a reversible 2-to-4 decoder in quantum-dot cellular automata using Toffoli gates

This research presents an optimized design of a 2-to-4 decoder in Quantum-dot Cellular Automata (QCA) using a new formula developed from the Reversible. The proposed QCA decoder architecture employs 112 cells and occupies an area of 0.13μm², achieving a significant reduction in size compared to previous designs. The circuit is designed using a single-layer approach, enhancing its efficiency and minimizing power dissipation. Simulation results using the QCA Designer simulator version 2.0.3 demonstrate the enhanced functionality of the suggested decoder in regard to functionality and also efficiency, making it a promising candidate for future nanoscale integrated circuit applications.

Implementation of EXOR and Subsequent Modular Circuits for Application at Nanoscale Level

Evolving as an outperforming nanotechnology, quantum-dot cellular automata (QCA) is being efficiently used for the design and development of digital modules. This paper presents a novel design for an ultra-efficient exclusive-OR (EXOR) gate in QCA nanotechnology using the cell translation technique. The analysis for fault tolerance and power dissipation of the proposed design is also assessed. To establish the effectiveness of the proposed design, an extensive comparison with the existing designs is provided. As a test bench implementation, the proposed EXOR gate is available as a module for the development of a parity checker, a full subtractor, and a 4-input binary to gray (B2G) code converter in QCA. The cell count for the proposed design of the EXOR gate, full subtractor, parity checker, and 4-input B2G converter is 8, 35, 24, and 24, and the total area (µm2) is 0.0039, 0.0259, 0.01749, and 0.0129, respectively. The proposed EXOR gate design outclasses the hitherto prevailing designs both in terms of the operational parameters and the dissipation of energy. The design simulations have been performed in QCA Designer 2.0.3, and the energy dissipation analysis has been executed in QCA Designer-E and QCAPro.

Reliable Synchronous and Asynchronous Counter Design in QCA

Due to rapid growth in the integrated circuit (IC) industry, the demand for compact digital system design is high. However, the continued technology reductions made the feasibility of further scaling down transistor size more challenging. In response to the growing demand for ultra-compact IC designs, the revolutionary quantum-dot cellular automata (QCA) technology has emerged as a promising solution. In a digital era, the counters are widely adopted in the peer-to-peer process flow to establish a mechanism for generating unique values for each identifier/number. In this work, a unique synchronous and asynchronous counters architecture is proposed with a reliable D and T flip-flop design. The proposed QCA architecture is implemented and validated with the QCA designer tool. Furthermore, in QCA technology, unreliable QCA designs can lead to frequent errors and malfunctions in the implemented logic. To overcome this challenge, the proposed design prioritizes cell placement (the relative positions of QCA cells) to make the circuit more robust. As a result, the circuit can still produce the expected functionality even if some QCA cells malfunction. Hence, to ensure the reliability of the proposed QCA architecture, the missing cell defect analysis is carried out in comparison with existing state-of-the-art designs. Based on comparison results, the unique designs like the proposed multiplexer, D flip-flop and T flip-flop design exhibit success rates of 67.28, 77.04 and 85.15%, respectively. The experimental results demonstrate that the proposed counter-architecture outperforms existing architectures.

Reversible arithmetic and logic unit using a novel reversible NRRG gate in quantum dot technology

Quantum-dot Cellular Automata (QCA) has become one of the promising studies for nano-scale computing. QCA is one of the candidate technologies to be replaced with CMOS technology. QCA technology not only reduces power consumption and delay but also increases operating frequency and speed. The arithmetic logic unit is the essential component in a processor that performs arithmetic and logical operations. This paper presents a novel 5 × 5 reversible logic gate called the NRRG (Norouzi_Rasouli Reversible Gate) which can be used as the basic building block of 4:1 and 8:1 reversible multiplexers. Then, we have designed a RALU (reversible arithmetic and logic unit) using this gate. Our design can perform 20 operations such as AND, NAND, OR, XOR, XNOR, COPY, addition, and increment. The proposed QCA RALU requires 0.44 μm2 area, 480 QCA cells, and 10 clock phases. The proposed design needs less cell count, delay, and cost of QCA compared to previous works. The structure is implemented without any rotated cells and only uses one layer which improves the manufacturability of the design. The architectures are designed and simulated using QCA Designer 2.0.3.

Design and Implementation of a 2-input Arithmetic and Logic Unit using Quantum-dot Cellular Automata

Quantum-Dot-Cellular Automata (QCA), an emerging nanotechnology rooted in Coulomb repulsion, holds the ability to supplant orthodox complementary metal-oxide semiconductor (CMOS) technology. Its distinctive advantages lie in ultra-low power consumption, fast switching speed, and high-density structures. This study conducts an extensive literature review to introduce an Arithmetic and Logic Unit (ALU) based on QCA principles. The proposed QCA-based ALU incorporates fundamental logic gates, adders, and subtractors, leveraging the latest XOR gate. Utilizing simulation via QCA Designer 2.0.3, an in-depth performance evaluation of the model is conducted, comparing it with established ALUs based on metrics encompassing cell count, delay, and area. The findings showcase the efficiency of the proposed ALU, characterized by its minimal requirement of 277 cells, an area occupancy of 0.43 µm², and a delay of 2.75 clock cycles. This outcome highlights the favorable attributes of our design compared to existing alternatives, suggesting its potential contribution to the advancement of QCA-based digital circuitry. DUJASE Vol. 8 (1) 26-31, 2023 (January)

Quad-functioning parity layout for nanocomputing: A QCA design

Quantum dot cellular automata (QCA) is considered an alternative to conventional technologies like CMOS (Complementary Metal-Oxide-Semiconductor) technology due to its potential for lower power consumption, higher speed, and increased device density. QCA introduces a novel approach to designing nano communication circuits and systems. Nano communications data mistakes are detected via parity generators and checkers. The parity bit of each data block ensures that the number of 1′s is either even or odd. Consequently, the system requires four circuits: an even parity generator, an odd parity generator, an even parity checker, and an odd parity checker. The whole system requires more space and cell complexity. In this work, we propose a QCA architecture that serves as a generator for both even and odd parities, as well as a checker for both even and odd parities. It is a quad-functioning circuit that performs four distinct operations within a single design, utilizing 118 QCA cells and occupying an area of 0.17 μm2. The recommended approach uses an efficient XOR gate, resulting in improvements across several performance metrics. QCAPro calculates energy dissipation and design parameters. The recommended QCA circuit outperformed similar QCA circuits in size, complexity, and energy dissipation. The circuit's design cost functions are also low. There has been a 17% reduction in latency and an 86% improvement in QCA-specific costs when compared to the optimal existing design. Moreover, it necessitates a 40% reduction in majority gate usage. The proposed design may compete effectively with other equivalent higher-order circuit designs by reducing the need for multiple blocks in conventional circuits to execute the same task. This architecture holds potential benefits for nano processors and nano communication networks.

Design of energy, cost-efficient binary to gray code converter with temperature and stability analysis

The Quantum Dot Cellular Automata (QCA) is an emerging quantum electronics technology in which quantum cells are the fundamental building blocks. In this work, a Binary to Gray (BTG) code converter design is proposed and implemented using the QCA Designer Tool. This code converter design requires fewer cells than earlier designs and also increases the converter’s implementation bit size to five. The primary objective of this proposal is to introduce a BTG code converter design that excels in temperature stability and energy efficiency. The cell count in the proposed converter design for two-bit, three-bit, and four-bit is decreased by 68.55 %, 66.52 %, and 67.77 %, respectively and the overall area improved by 46.15 %, 52.17 %, and 57.58 % for 2- bit,3-bit and 4-bit, respectively by considering a latency of 0.75. The five-bit BTG has an area of 0.20 µm2 with a cell count of 141 and a latency of 0.75. To validate the functionality of the proposed design, extensive simulations were carried out using the QCA Designer tool, QCA DesignerE tool, and QCA Pro tool respectively.

Design of QCA based memory cell using a novel majority voter with physical validation

Quantum Dot Cellular Automata (QCA) is a unique transistor less paradigm which effectively uses change in cell polarization to perform logical operations with high speed, low power and high intricacy. In recent years, the need of high performance memory cell is increased for improving the system performance. This paper presents the design of a QCA based memory cell with read write capabilities. In recent past, most of the QCA circuits are designed using the conventional three input majority voter. The conventional three input majority gate is not fault tolerant. Thus, we need an alternative design which can serve as the majority voter and also shows the fault tolerance. Moreover, the design of three input majority voter is not much addressed . In this paper, an alternative, simple structure of three input majority voter is presented which is better than the conventional one in terms of fault tolerance. In addition to this, the proposed three input majority voter is power aware and efficient to realize various digital circuits. The correctness of the proposed majority voter is validated through the physical proof. Moreover, the proposed gate is subjected to cell displacement defect to investigate the testability. The proposed gate is further used to implement rudimentary elements such as XOR gate, multiplexer and D latch. Finally, the design of Random Access Memory (RAM) cell with read, write, set and reset capabilities is proposed using the presented majority voter. The proposed circuits are further subjected to comprehensive analyses for estimation of cost functions and energy dissipation. The investigation of presented circuits manifests the use of proposed majority voter for next generation computing circuits.

Development of a high-performance arithmetic and logic unit for efficient digital signal processing based on reversible logic and quantum dots

Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas.

Ultra-optimized demultiplexer unit design in quantum-dot cellular automata nanotechnology

Integrated circuit designers face challenges in using complementary metal oxide semiconductor (CMOS) technology as it has a large leakage current and scalability challenge in ultra-nanoscale regime. Quantum-dot Cellular Automata (QCA) is a nanotechnology that can replace CMOS for designing ultra-deep submicron circuits and overcoming CMOS limitations. In this research paper, a novel area-efficient 1:2 demultiplexer is proposed using QCA technology. A demultiplexer is an important combinational circuit used in communication systems and computer memories. It receives serial input data and routes data in parallel to multiple outputs. QCA Designer and QCA Pro-tools are used for layout, simulation, and analysis of power dissipation. 11 QCA cells are utilized in the construction of the proposed 1:2 demultiplexer. The cell area and layout cost of the proposed demultiplexer have improved to 42.11 % and 55.56 % of the current best design, respectively. An essential factor to consider when developing integrated circuits is power dissipation. The proposed design dissipates less power. The energy dissipation of the proposed design has improved to 57.67 % at the kink energy level of 1.5 of the current best design.

Efficient Nano-Scale Design of TIEO Based Reversible Logic Toffoli Gate Priority Encoder in Quantum-Dot Cellular Automata

The goal of this research is to create a QCA-based reversible priority encoder. It is one of the most crucial parts of the encoding and decoding process. This novel nanotechnology, known as quantum-dot cellular automata (QCA), shows promise as a foundation for the development of reversible circuits. This paper proposes a simple, reversible, 4-2 line priority encoder design for the QCA platform. Using the simple and cheap Toffoli gate architecture, a reversible encoder circuit may be built. To analyze the proposed designs’ structural soundness, the simulation program QCA Designer is used.

An Efficient Design of a Parallel Prefix Adder based on QCA Technology

This paper presents an optimized Parallel Prefix Adders (PPA) based on Quantum dot Cellular Automata (QCA) technology. PPA presents the most used block in Arithmetic Logic Units (ALU) which presents a fundamental part in several digital integrated circuits. The classical implementation method of PPA based on traditional Complementary Metal Oxide Semiconductor (CMOS) Technology presents several problems in terms of frequency, power consumption, surface and others. The QCA technology offers several features such as ultralow power consumption, small size, and can operate up to 1 THz. In this work, a 4-bit Parallel Prefix Adder with a new prefix low area and high speed is proposed. The proposed design is based on a half-adder circuit and other logic gates. These designs were tested and simulated using the freely known QCA Designer Tool version 2.0.3. and QCA pro. The proposed Half-adder presents a reduction of 23% 46% and 36% in terms of cell count, latency and power consumption, respectively compared to existing designs. The proposed PPA design shows almost an optimization of 5% in area and 58% in latency compared to the RCA design. The proposed circuit present an optimization of 20% in term of energy consumption compared to the existing PPA 4-bit Brent Kung Adder design.

QCA-Based Design of Novel Low-Power n-Bit Ripple Carry Incrementer and Ripple Carry Decrementer

This study demonstrates the development of an innovative [Formula: see text]-bit less power ripple carry incrementer (RCI) and decrementer (RCD) circuit, respectively, devised using quantum dot cellular automata (QCA). In order to increment or decrement two numbers, RCI and RCD are essential. With a revised configuration of the AND gate, half adder, and XOR gate circuit, the suggested ripple carry incrementer and decrementer circuits are realized. Modern designs for the XOR and half adder are contrasted with these freshly created ones. Circuits are designed using QCA designer 2.0.3. The 4-bit RCI, 8-bit RCI, and 16-bit RCI as well as 4-bit RCD, 8-bit RCD, and 16-bit RCD simulation results are compared to the theoretical findings.

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is a novel nano-electronic technology. QCA has attracted wide attention due to its extremely small feature sizes at the molecular or even atomic scale and ultra-low power consumption, making it a promising candidate to replace the complementary metal oxide semiconductor (CMOS) technology. Binary-Coded Decimal (BCD) adders are widely used in industrial computing. In this paper, we propose two types of excess-3 code (XS-3) based BCD adders (XS-3DAs). We use ripple-carry adders (RCA) and parallel binary adders (PBA) to construct XS-3DAs in QCA Designer tool, respectively. The PBA-based XS-3DA is constructed with a new correction logic. 4-bit, 8-bit, and 16-bit XS-3DAs are constructed based on the two proposed XS-3DAs, respectively. Comparisons show that, with the increase of design scaling, the delay and area-delay product (ADP) of the PBA-based XS-3DAs can be significantly reduced in comparison with that of the RCA-based XS-3DAs. Compared with the 16-digit RCA-based XS-3DA, the cell count, area, delay and ADP of the proposed 16-digit PBA-based XS-3DA are reduced by 37.88%, 25.99%, 37.68% and 53.88%, respectively.

Design of BCD Adder Using QCA Technology

Abstract: Quantum-dot Cellular Automata (QCA) technology is a promising alternative to traditional complementary metaloxide-semiconductor (CMOS) technology for implementing digital circuits due to its potential for high speed, low power consumption, and small size. In this paper, we present a design for a Binary Coded Decimal (BCD) adder using QCA technology. The BCD adder is a crucial building block for arithmetic operations in decimal representation. The proposed design uses QCA cells to perform the addition operation of two BCD digits, which are encoded as a 4-bit binary number. The design includes a full-adder circuit, a BCD-to-binary converter, and a carry-lookahead adder. Simulation results using QCA Designer software demonstrate the functionality and feasibility of the proposed BCD adder design. The proposed design provides a promising alternative to traditional CMOS-based BCD adders and can contribute to the development of QCA-based digital circuits

A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs), especially with memories of multiple valued logic (MVL) in nanotechnologies. FinFET technologies provide the possibilities of low logic gates and small chip areas with high speed. Memories play an essential role in all types of devices. This paper aims to optimize the power and increase the speed of the SRAM Cell and Array using different techniques in 18nm FinFET technology. The presence of a ternary input provides an additional degree of freedom for the operation of the memory cell. The SRAM cells are also implemented at a Quantum level to improve the results in terms of area, energy, and speed. Simulation and Analysis of the design is done using Cadence Virtuoso Analog Design Environment Tool and Quantum Dot Cellular Automata Designer Tool. The proposed Multi-Threshold Complementary MOS (MTCMOS) based SRAM Array design exhibits an improvement of 4.56% in power consumption and 19.29% in speed as compared to a Conventional CMOS SRAM Array. The proposed ternary implementation of the MTCMOS-based SRAM cell is found to have a 24.9% reduction in power consumption and a 39% improvement in speed as compared to the proposed conventional ternary CMOS SRAM array while SRAM cell latency is 1 clock cycle. It occupies an area of 0.04 µm2 and consists of 33 quantum cells. The average energy dissipation of this SRAM cell is found to be 40% better than the latest existing literature for the design.

Design of QCA based N-bit single layer shift register using efficient JK Flip Flop for nano-communication applications

Quantum-dot Cellular Automata (QCA) is a technology that has the potential to create nano communication systems that are both highly efficient in power consumption and compact in size When compared to CMOS enabled electronic devices, QCA can achieve faster operation speed, higher density and lower power dissipation which becomes a boon, in digital logic design. In this paper, proposed work of designing sequential circuits using QCA has been achieved. An efficient JK flip-flop design along with 2-bit, 3-bit, 4-bit and 8-bit shift registers which can be further scaled up to N-bits using the same proposed design of flip-flop is observed. Also, the fault tolerance of proposed JK flip-flop design against single cell addition and deletion defects are presented in this paper. After conducting a performance comparison and thorough analysis of energy dissipation, it has been determined that the proposed designs bear lower cost and lower energy dissipations. Using QCADesigner tool, the validation of functions and processes of all proposed sequential designs has been done accordingly.

New Methodology for the Design of Nanostructured Integrated Circuits

Background: A metal oxide semiconductor field effect transistor (MOSFET) is widely used to make integrated circuits (ICs). MOSFET devices are reaching the practical limitations for further scaling in the nanoscale regime. It motivates the researchers to explore and develop new ways to advance the electronics industry. Quantum-dot cellular automata (QCA) is a potential way to replace the MOSFET devices in the nanoscale regime. QCA nanotechnology not only solves the issue of scalability but also degrades the leakage current. It has numerous benefits, such as a highly dense design, fast speed, and energy efficiency compared to complementary metal-oxide-semiconductor (CMOS) technology. Objective: An extensive study of QCA nanotechnology is needed to quickly understand the field. Optimizing the QCA designs is the mandatory requirement to minimize the occupied cell area, latency and quantum cost. The preliminary knowledge of QCA nanotechnology boosts the idea of generating different logic functions. This review paper presents the methodology for making the fundamental logic gates using QCA nanotechnology. XOR gate is commonly used to implement popular circuits such as adders, subtractors, comparators, code converters, reversible gates etc. The various available QCA-based 2-input XOR gate designs are discussed and compared for the different performance metrics. Methods: Columbic interaction causes logical operations, and data is transferred from one cell to another cell using cell-to-cell interaction. A specific arrangement of QCA cells produces a specific logic. QCA Designer tool using a Bi-stable simulation engine is used to design different digital circuits. Results: This review paper deals with the design of the 2-input XOR gate. The considered performance metrics for the comparison purpose are cell count, occupied area, clock cycle, and quantum cost. Existing works on 2-input XOR gates show that a minimum of 8 QCA cells are needed for a 2-input XOR gate using QCA nanotechnology. A single clock cycle-based 2-input XOR gate requires at least 9 QCA cells. The quantum cost can be minimized by reducing the number of QCA cells and clock cycles. Conclusion: This review paper helps the circuit designers to select the appropriate 2-input XOR gate for the design of complex circuits. Circuit designers can use the fundamental concepts detailed in the paper to implement any Boolean function and optimize it for the existing designs. A researcher had developed a 2-input XOR gate using only 8 QCA cells with 0.50 clock cycles. Therefore, designers can start from here to further optimize the 2-input XOR gate with a single clock cycle.

A novel QCA circuit-switched network with power dissipation analysis for nano communication applications

Today, communication links and networks are essential in transmitting data and information. Moreover, information sharing in communication devices and networks has become necessary, routine, and unavoidable. Consequently, designing and manufacturing high-speed nano-scale devices with ultra-low power consumption is very important. Among the emerging paradigms in nanotechnologies, quantum-dot cellular automata (QCA) is very popular in communication sciences. In the present study, we optimize the design and implementation of a QCA crossbar switch and use it in transmitter and receiver circuits. Subsequently, a circuit-switched network in QCA technology is implemented using these devices. All the designed circuits are coplanar with the minimum number of cells, optimal area and latency, and low power consumptions, which employ standard QCA design rules and show superiority and advantages compared to the previous designs.

Novel Quantum-Dot Cellular Automata-Based Gate Designs for Efficient Reversible Computing

Reversible logic enables ultra-low power circuit design and quantum computation. Quantum-dot Cellular Automata (QCA) is the most promising technology considered to implement reversible circuits, mainly due to the correspondence between features of reversible and QCA circuits. This work aims to push forward the state-of-the-art of the QCA-based reversible circuits implementation by proposing a novel QCA design of a reversible full adder\full subtractor (FA\FS). At first, we consider an efficient XOR-gate, and based on this, new QCA circuit layouts of Feynman, Toffoli, Peres, PQR, TR, RUG, URG, RQCA, and RQG are proposed. The efficient XOR gate significantly reduces the required clock phases and circuit area. As a result, all the proposed reversible circuits are efficient regarding cell count, delay, and circuit area. Finally, based on the presented reversible gates, a novel QCA design of a reversible full adder\full subtractor (FA\FS) is proposed. Compared to the state-of-the-art circuits, the proposed QCA design of FA\FS reversible circuit achieved up to 57% area savings, with 46% and 29% reduction in cell number and delay, respectively.