Quantum-dot Cellular Automata Design Research Articles

Quantum-Dot Cellular Automata Technology for High-Speed High-Data-Rate Networks

In today’s technology, optical networking plays a vital role in reducing data losses, thereby providing higher data rates between the transreceivers. The very large scale integration circuits in the modulator–demodulator (MODEM) usually fabricated using complementary metal oxide semiconductor (CMOS) technology have serious scaling limitations; hence, device scaling beyond 65 nm technology becomes highly challenging. Quantum-dot cellular automata (QCA) is one of the most promising nanotechnologies that enable areas of smaller size, i.e. 60% less design area than the CMOS technology, with capability to produce high speed by taking less cycles compared with the other CMOS designs to reduce scaling issues. The QCA-based designs are considered as the best alternative solutions to the transistor-based (CMOS) designs. This paper deals with the implementation of the logic gates NOT, AND, OR, NAND, NOR, XOR and XNOR using both CMOS and QCA technologies, while the QCA allows more possible design structures for each logic gate to enable optimization of the area. Finally, the proposed QCA-based logic gate design and CMOS-based designs are compared in terms of the design area, cell count and the speed of the designs. QCA designer 2.0.3 and virtuoso CADENCE Computer-Aided Design tools are used for carrying out the work.

New efficient designs of reversible logic gates and circuits in the QCA technology

Quantum-dot cellular automata (QCA) is a developing nanotechnology, which seems to be a good candidate to replace the conventional complementary metal-oxide-semiconductor (CMOS) technology. The QCA has the advantages of very low power dissipation, faster switching speed, and extremely low circuit area, which can be used in designing nanoscale reversible circuits. In this paper, the new efficient QCA implementations of the basic reversible Gates such as: CNOT, Toffoli, Feynman, Double Feynman, Fredkin, Peres, MCL, and R Gates are presented based on the straight interactions between the QCA cells. Also, the designs of 4-Bit reversible parity checker and 3-bit reversible binary to Grey converter are introduced using these optimized reversible Gates. The proposed layouts are designed and simulated using QCADesigner software. In comparison with previous QCA designs, the proposed layouts are implemented with the minimum area, minimum number of cells, and minimum delay without any wire-crossing techniques. Also, in comparison with the CMOS technology, the proposed layouts are more efficient in terms of the area and power. Therefore, our designs can be used to realize quantum computation in ultralow power computer communication.

Ultra-efficient convolution encoder design in quantum-dot cellular automata with power dissipation analysis

Nowadays, Quantum-dot Cellular Automata (QCA) is a well-known technology for designing digital systems. Actually, QCA is the most possible alternative for semiconductor transistor based technology. In this paper, an improved design of QCA based convolution encoder has been proposed. The proposed encoder outperforms previous QCA based design from the view of size, speed, and power consumption. A popular simulator, QCADesigner has been used for simulating and verifying the proposed encoder. Simulation result shows proposed encoder’s dominance against previous designs from the context of cell number, area, latency, and energy consumption. The proposed 1/2 rate and 1/3 rate encoder reveal 89% and 85% less energy consumption at 0.5Ek tunneling energy level as compared to the previous design. It is worth mentioning that 90% and 86% optimizations in the number of cells in addition to 95% and 96% optimizations in the area are achieved for the proposed 1/2 rate and 1/3 rate convolution encoder, respectively, in comparison with the previous design.

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

New designs of fault-tolerant adders in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has attracted attention as one of the best forms of alternative Nanoscale CMOS technology. It has facilitated the designing of digital circuits with high density and speed. One of the important issues in QCA technology is designing fault-tolerant digital circuits. QCA-based circuits frequently suffer from fabrication and unstable faults: these make them unreliable and susceptible to breakdown. In this paper, two new fault-tolerant 3-input majority gates have been proposed in QCA technology. The robustness of the proposed structures has been evaluated in terms of defects such as cell omission, deposition of extra cell and cell displacement defects. The simulations were performed using the QCA Designer 2.0.03 and QCAPro tools to measure performance and energy consumption. The obtained results indicate that the proposed structures benefit from higher fault-tolerant in comparison to previous designs. Moreover, we provided four new fault-tolerant full-adders and a multi-bit adder using the proposed structures and acceptable results are archived.

A Novel Full Adder/Subtractor in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA), one of the alternative CMOS technologies at a nano scale, promises to design digital circuits with extra low-power, extremely dense and high speed structures. In this paper, a new QCA gate with three inputs and two outputs is first introduced; this operates on the basis of cell interactions. Then, low complexity and high-speed QCA full-adder and full-subtractor structures are proposed by applying different formulations, which are based on the introduced gate. Finally, a novel QCA full adder/subtractor is presented with the synergy of the proposed QCA full-adder and full-subtractor structures as well as a proposed optimal single layer 2:1 QCA multiplexer. The proposed designs are simulated using the QCA Designer 2.0.3. The simulation results confirm that the proposed circuits work well. A comparative analysis indicates the superiority of the proposed designs compared to the other related designs. Moreover, the QCAPro power estimator tool is utilized to evaluate the power dissipation of the proposed designs.

Towards modular binary to gray converter design using LTEx module of quantum-dot cellular automata

A modular approach to realize the ultra-fast quantum-dot cellular automata (QCA) generic binary to gray converter is presented in this paper. The novel designs here validated fully exploit the intrinsic repetitive capabilities of the Layered T Exclusive OR (LTEx) module in the QCA domain. An efficient logic formulation of QCA design metrics like O-Cost and delay is proposed for the n-bit QCA binary to gray converter designs. The QCA implementation of n-bit LTEx binary to gray converter is compared with the conventional converters. An attempt has been made to enhance the speed of modular binary to gray converter designs. The proposed 4, 8, 16, 32, 64-bit binary to gray converters need 4.35, 15.88, 15.96, 15.7, 16.68% less O-cost and 11.57, 2.61, 9.32, 12.64, 29.25% less effective area, respectively. Thus the proposed layouts offer the smaller feature size, reduced circuit complexity exploiting the modular based design approach. The simulation results have been carried out in the renowned computer aided design tool, namely QCADesigner 2.0.3 with gallium arsenide heterostructure based parameter environment.

An optimal design of conservative efficient reversible parity logic circuits using QCA

Quantum-dot Cellular Automata (QCA) is a new nano-innovation in digital systems. It is a possible alternative to ordinary CMOS technology. It offers several advantages in reversible logic such as small size and low power dissipation. Therefore, lots of attentions have been paid to implement different reversible QCA circuits. In this way, an improved model of low power odd-parity-bit, generator and checker have been proposed based on the reversible Feynman gate. The proposed reversible odd-parity-bit, generator and checker can be used to check/detect bit loss of information in telecommunication network systems. The proposed parity generator is 57% faster and occupies 38% lesser area than the previous best design. Furthermore, the proposed Nano-communication system dissipates 65% less energy at 0.5 Ek tunneling energy level. A detailed performance evaluation and power analysis are performed in different aspects to authenticate our proposed bit preservation circuits have superb performance in comparison to previously reported works. The results of the proposed circuits have been verified using QCA Designer and the power calculations have been carried out using QCA Pro tool.

Efficient design of BinDCT in quantum‐dot cellular automata (QCA) technology

Here, the authors present a hardware design of fast multiplierless forward binary discrete cosine transform (BinDCT) based on quantum-dot cellular automata (QCA) technology. This new technology offers several features such as: small size, ultralow power consumption, and can operate at 1 THz. The simulation results in QCA Designer software confirm that the proposed circuit works well and can be used as a high-performance design in QCA technology. The analysis obtained from the implementation of QCA BinDCT indicates that the proposed architecture is superior to the existing based on classic metal-oxide (complementary metal-oxide semiconductor technology) technology. Here, the authors are going to introduce highly BinDCT module scaled with ultra-low power consuming. The proposed circuit requires 50% fewer power consuming compared to previous existing designs. The proposed architecture can attain a throughput of 800 mega pixel per second (Mpps). To design and verify the proposed architecture, QCADesigner tool and QCAPro tool are, respectively, employed for synthesis and power consumption estimation. Since the works in the field of QCA logic image processing have only started to bloom, the proposed contribution will engender a new thread of research in the field of real-time image and video treatment.

Designing Efficient Configurable QCA Nano Circuit for Morphological Operations in Image Processing

Morphological operations like erosion and dilation are important operations in various video and image processing applications. This research presents a configurable Quantum-dot Cellular Automata (QCA) nano circuit for morphological applications in image processing. QCA is a field-coupled emerging nano-technology which can be applied in various image processing operations. The implemented QCA design utilizes two cascaded 5-input majority voters where dilation and erosion can be performed with the help of a control line. The proposed design is compared with the previous results which demonstrate substantial improvement in terms of area, delay and cell count.

QCA BASED SECURE NANOCOMMUNICATION BLOCK CIPHER DESIGN BASED ON ELECTRONIC CODE BOOK

In nanotechnology, Quantum Dot-Cellular Automata (QCA) is a new paradigm that can serve as an alternative to CMOS circuits. In comparison to CMOS, QCA has lower device area and faster processing power with an overall low energy consumption. The complexity of cryptographic architecture is a key issue in terms of circuit density and power dissipation.Moreover, security is the major issue in nanocommunication systems. Those issues can be overcome through QCA technology. To date, only few applications of QCA have been explored in the field of cryptography. This paper illustrates the QCA design and implementation of block cipher based on electronic code book (ECB). An encoder circuit, which can function as decoder for ECB is proposed. The design requires only 0.095 I¼m2 area and a latency value of 0.75. The circuit dissipates very low energy which is established through calculation of power dissipation. Due to inherent characteristics, side channel attacks like power analysis attack can be prohibited using proposed circuit. The circuit is implemented on QCA Designer platform and the design accuracy is verified via simulation results.

QCA Gray Code Converter Circuits Using LTEx Methodology

The Quantum-dot Cellular Automata (QCA) is the prominent paradigm of nanotechnology considered to continue the computation at deep sub-micron regime. The QCA realizations of several multilevel circuit of arithmetic logic unit have been introduced in the recent years. However, as high fan-in Binary to Gray (B2G) and Gray to Binary (G2B) Converters exist in the processor based architecture, no attention has been paid towards the QCA instantiation of the Gray Code Converters which are anticipated to be used in 8-bit, 16-bit, 32-bit or even more bit addressable machines of Gray Code Addressing schemes. In this work the two-input Layered T module is presented to exploit the operation of an Exclusive-OR Gate (namely LTEx module) as an elemental block. The “defect-tolerant analysis” of the two-input LTEx module has been analyzed to establish the scalability and reproducibility of the LTEx module in the complex circuits. The novel formulations exploiting the operability of the LTEx module have been proposed to instantiate area-delay efficient B2G and G2B Converters which can be exclusively used in Gray Code Addressing schemes. Moreover this work formulates the QCA design metrics such as O-Cost, Effective area, Delay and Cost α for the n-bit converter layouts.

An efficient design of Quantum-dot Cellular Automata based 5-input majority gate with power analysis

Quantum-dot Cellular Automata (QCA) are among the alternative technologies that enable nanoscale circuit design of high performance and low power consumption features. This work showcases an extensive structural and power analysis of previous 5-input majority gates. We found that the existing 5-input majority gates are not power efficient, and the structures are not well optimized. To overcome this, we proposed a new low-complexity coplanar 5-input majority gate, which consumes less power compared to prior designs. A novel 1-bit full adder circuit is presented to evaluate the suitability of the proposed gate. The results demonstrate that the proposed full adder performs equally well compared to existing multilayer designs, and performs better in the case of previous coplanar full adder designs in all aspects. Our design achieves 22% reduction in cell count and takes 18% less area in comparison to the best single layer design. Furthermore, it produces an equal delay, when compared to the best design in this segment. The QCADesigner tool is used to validate the layout of the proposed designs and the QCAPro power estimator tool is used to evaluate the power dissipation of all considered designs. Our results clearly demonstrate that, the hardware requirement for a QCA design is reduced and circuits become simpler in level, gate counts and clock phases by considering proposed gate.

Design and implementation of crossbar scheduler for system‐on‐chip network in quantum dot cellular automata technology

System‐on‐chip (SoC) provides a comprehensive solution to the design challenges involved in the domain of telecommunication network, multimedia, and consumer electronics. One of the crucial components of any SoC network is the crossbar‐based switching circuit which synchronizes the network traffic and provides a congestion‐free path for communication. With the increase in number of on‐chip components the power consumed by crossbar schedulers takes a significant amount of the entire power budget. This indicates the need for techniques to reduce the area and energy consumption of on‐chip schedulers. In this article, we have proposed the design of on‐chip schedulers for implementation in quantum dot cellular automata (QCA) technology. QCA is the latest nano computation technology and emerging as an alternative to replace the conventional CMOS devices. The salient features of QCA are highly dense structure, extremely low power consumption, and very high processing speed. The proposed on‐chip scheduler circuit has been simulated using QCA designer tool. To perform a fair comparison, we also synthesized the proposed design in CMOS technology. The results obtained from comparison indicate that the QCA circuits occupy less area and power consumption than the traditional CMOS technology.

Design of Generalized Pipeline Cellular Array in Quantum-Dot Cellular Automata

Cellular arrays have been the topic of interest in computer arithmetic and architecture for the last four decades. In this letter, an overall quantum-dot cellular automata (QCA) design for a generalized pipeline cellular array is presented. QCA is one of the promising emerging nanotechnologies that are being considered as possible alternatives to complementary metal-oxide semiconductor technology due to the physical limitations of CMOS. The QCA designs for arithmetic cell and control cell used in the pipeline array are discussed in detail. The equivalent majority logic networks to these cells are generated using the best existing majority logic synthesis method in order to obtain the optimal majority networks which require fewer QCA cells and clock zones compared to other synthesis methods. The proposed array can perform all the basic arithmetic operations such as squaring, square rooting, multiplication, division, etc., which could be quite valuable in considering future large-scale QCA designs.

Study and Performance Analysis of MOS Technology and Nanocomputing QCA

One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.

An optimized design of full adder based on nanoscale quantum-dot cellular automata

Quantum-Dot Cellular Automata (QCA) technology uses quantum dots instead of transistors and diodes for performing the logical operation. Also, in logical circuits, many operations, such as multiplication, subtraction, and division are done using the adders. Therefore, this paper presents an efficient QCA-based adder design based on three layers. In contrast to the previous designs, the outputs in the proposed design come out from another side of the circuit which causes more efficient circuit design. In the proposed design, the input signals are not surrounded by the other cells and can easily be accessed. The simulation results using the QCA Designer approve that the offered circuit acts well and can be used as a high-performance design in the QCA. Also, they show that the design causes very low complexity, small area, short latency and fewer cell numbers.

Innovative model for ternary QCA gates

Implementation of basic ternary logic gates is more complex than binary gates in quantum-dot cellular automata (QCA) technology. Several models have been presented for designing ternary logic gates. Most of these models are different solutions and are based on manual calculations. It seems that no simulation tool for designing ternary QCA (tQCA) logic gates has been presented. Unlike previous works, this study is an attempt to introduce an alternative model and the related software for tQCA logic gates. Prominent basic ternary logic gates - such as Min gate, Max gate and inverter - are proposed and simulated in the newly designed TQCAsim software which is an accurate simulation and design tool and is based on the algorithm proposed in this study. Unlike QCA designer software, which has been designed for binary QCA, TQCAsim is designed exclusively for tQCA. Thus, this software can be used to verify and implement the proposed tQCA gates and even earlier designs.

An optimal design of QCA based 2n:1/1:2n multiplexer/demultiplexer and its efficient digital logic realization

Quantum-Dot Cellular Automata (QCA) is a radical nanotechnology, which works at Nanoscale. In this paper, an optimal design of 2n:1 Multiplexer (MUX) and 1:2n Demultiplexer (DeMUX) is presented. A new approach has been devised to implement efficient digital logic gates using the proposed 2n:1 multiplexer. To verify the functionality of the proposed structures some Boolean proofs are performed. A detailed comparison, structural evaluation and power analysis of the proposed multiplexer with recently robust designs are analyzed. This evaluates the performance of the proposed multiplexer in terms of cell count, area clock delays and energy dissipation as compared to traditional approaches. At temperature T = 2k, the energy dissipation is evaluated under the three separate tunneling energy levels (γ=0.5Ek,γ=1.0,Ek andγ=1.5Ek). New implementation and simulation results of the proposed 4n:1MUX and 1:4n DeMUX are developed using the proposed 2:1 MUX and 1:2 DeMux respectively. In addition, a novel concept of QCA based Multiplexing/Demultiplexing is presented. This paves way sharing a single communication link among the number of devices at nano-regime.

Efficient Design of Exclusive-Or Gate using 5-Input Majority Gate in QCA

Quantum dot cellular automata (QCA) is one of the emerging technology that has the capability of replacing the CMOS based technology at nano scale level. Majority gates and inverter are the principle elements in QCA to design any circuit. In this work, we propose a new 5-input majority gate. The new proposed gate reduces number of required cell, area and power consumption. The study of power dissipation is also explained using power estimator tool QCAPro. QCA designer 2.0.3 is used to validate the majority gate layout and their functionality. Furthermore, an XOR gate based on QCA are designed using proposed majority gate. Layout and simulation results show the improvement of proposed circuit over previous designed circuits.