Quadrature Voltage Research Articles

Digital Simulation of the Generalized Unified Power Flow Controller System with 60-Pulse GTO-Based Voltage Source Converter

The Generalized Unified Power Flow Controller (GUPFC) is a Voltage Source Converter (VSC) based Flexible AC Transmission System (FACTS) controller for shunt and series compensation among the multiline transmission systems of a substation. The paper proposes a full model comprising of 60-pulse Gate Turn-Off thyristor VSC that is constructed becomes the GUPFC in digital simulation system and investigates the dynamic operation of control scheme for shunt and two series VSC for active and reactive power compensation and voltage stabilization of the electric grid network. The complete digital simulation of the shunt VSC operating as a Static Synchronous Compensator (STATCOM) controlling voltage at bus and two series VSC operating as a Static Synchronous Series Capacitor (SSSC) controlling injected voltage, while keeping injected voltage in quadrature with current within the power system is performed in the MATLAB/Simulink environment using the Power System Block set (PSB). The GUPFC, control system scheme and the electric grid network are modelled by specific electric blocks from the power system block set. The controllers for the shunt VSC and two series VSCs are pre- sented in this paper based on the decoupled current control strategy. The performance of GUPFC scheme connected to the 500-kV grid is evaluated. The proposed GUPFC controller scheme is fully validated by digital simulation.

Analysis and Design of Transformer-Based Dual-Band VCO for Software-Defined Radios

This work presents complete analysis of both one- port and two-port dual-band oscillators using transformer-based fourth-order LC tanks, from which critical parameters including oscillation frequency, start-up condition, tank Q, phase noise-are thoroughly derived and compared. It is shown that one-port oscillators consume less power than two-port counterparts but may suffer from stability problem which can be solved by a notch-peak cancellation technique. On the other hand, compared to one-port oscillators, two-port oscillators need to consume more power to obtain the same output swing, but their phase noise can be improved more linearly with increasing bias current, and thus they can achieve lower phase noise with a sufficiently large bias current. Based on the results, a dual-band quadrature voltage- controlled oscillator (Q-VCO) is systematically designed and implemented in a 0.13- m CMOS process for software-defined -radio (SDR) applications, in which the two-port topology is used in the low band for low phase noise and the one-port topology is employed in the high band for low power consumption. The prototype achieves a dual-band operation with in-phase and quadrature-phase (IQ) output signals from 2.7 GHz to 4.3 GHz and from 8.4 GHz to 12.4 GHz. At 3.6 GHz and 10.4 GHz, phase noise at 3 MHz offset of dBc/Hz and dBc/Hz and sideband-rejection ratios (SBR) of 37 dB and 41 dB are measured, respectively.

Inexpensive FM-CW Radar for Boundary-Layer Precipitation Studies

A vertically pointing C-band (5.8-GHz) frequency-modulated (FM) continuous-wave Doppler radar was developed for less than U.S. $6000, which can estimate the Doppler velocity power spectra from 20 to 300 m above the ground with a 5-m resolution. Three key design elements kept the costs low. First, the data acquisition system (DAS) commanded a direct digital synthesizer to start the FM sweep and then collected all voltage samples. This architecture insured phase coherence between the transmit FM sweep and the sampled voltages, which is critical for the Doppler processing that detects target phase changes over several successive FM sweeps. Second, a 5-m range resolution was achieved by increasing the FM bandwidth to over 36 MHz and decreasing the DAS sample rate to 500 kHz, enabling the use of an inexpensive DAS. Third, the Doppler processing at each range was achieved using two fast Fourier transforms (FFTs), i.e., a range FFT converted FM sweep voltages into in-phase and quadrature voltages I and Q at each range, and a Doppler FFT converted I and Q voltages from consecutive sweeps into the Doppler velocity power spectra. Observations show precipitation variability at 1-s and 5-m resolutions in the lowest 300 m of the atmosphere.

15 GHz quadrature voltage controlled oscillator in 130 nm CMOS technology

This paper reports a 15 GHz quadrature voltage controlled oscillator (QVCO) designed in a 130 nm CMOS technology. The phase noise performance of the QVCO and of a phase locked loop (PLL) where the QVCO was inserted were compared with the literature and with telecom standards and commercial products for broadcast satellite applications.

A second-harmonic LC-quadrature voltage controlled oscillator with direct connection of MOSFETs’ substrate

This work introduces a new low noise second-harmonic quadrature voltage controlled oscillator (QVCO) made by coupling two identical cross-connected LC voltage controlled oscillators. In each of the core oscillators the substrate nodes of the MOS varactors, and also the substrate nodes of the cross-connected MOSFETs are configured in such a way that they act as common mode nodes. Then the core oscillators are coupled together via direct connection of the substrates of the MOS varactors in one of the core oscillators to the substrates of the cross-connected MOSFETs in the other core oscillator, and vice versa. No extra elements are used for coupling of the two core oscillators and therefore no extra noise sources are imposed on the circuit. Operation of the proposed QVCO was investigated with simulation using a commercial 0.18 μm RF CMOS technology: it shows a power dissipation of 9.7 mW from a 1.8 V supply voltage and a simulated phase noise of ?125.5 dBc/Hz at 1 MHz offset from center oscillation frequency of 5 GHz. Since the tail transistor can be eliminated, the proposed QVCO can operate with supply voltages as low as 0.5 V, as confirmed with simulation.

Realization of electronically tunable voltage-mode/current-mode quadrature sinusoidal oscillator using ZC-CG-CDBA

This paper presents a first of its kind canonic realization of active RC (ARC) sinusoidal oscillator with non-interactive/independent tuning laws, which simultaneously provides buffered quadrature voltage outputs and explicit quadrature current outputs. The proposed circuit is created using a new active building block, namely the Z-copy controlled-gain current differencing buffered amplifier (ZC-CG-CDBA). The circuit uses three resistors and two grounded capacitors, and provides independent/non-interactive control of the condition of oscillation (CO) and the frequency of oscillation (FO) by means of different resistors. Other advantageous features of the circuit are the inherent electronic tunability of the FO via controlling current gains of the active elements and the suitability to be employed as a low-frequency oscillator. A non-ideal analysis of the circuit is carried out and experimental results verifying the workability of the proposed circuit are included.

CMOS second-harmonic quadrature voltage controlled oscillator using substrate for coupling

In this work, a new circuit configuration for second-harmonic quadrature voltage controlled oscillator (QVCO) with CMOS technology is proposed. The proposed QVCO is made by coupling two identical cross-connected VCOs. The coupling elements (two resistors and two capacitors) do not increase the power consumption of the core VCOs and do not disturb the resonant frequency of the tank circuit in the core VCOs and also, according to the simulations the coupling elements do not adversely affect the phase noise. The role of the substrate terminal of cross-connected MOSFETs of the core oscillators as common mode nodes is demonstrated. Using this node for coupling makes it possible to eliminate the tail transistors in the core oscillators and therefore the circuit can operate with supply voltages as low as 0.5 V. Using the same method to couple more than two core oscillators, results in a multiphase VCO.

Dual-band transformer-coupled quadrature injection-locked frequency dividers

This letter proposes a dual-band divide-by-2 transformer-coupled quadrature injection-locked frequency divider (QILFD).The QILFD is composed of a transformer-coupled quadrature voltage controlled oscillator and two injection MOSFETs. The CMOS QILFD has been implemented with the Taiwan Semiconductor Manufacture Company (TSMC) 0.18 μm CMOS technology, and the core power consumption is 3.997 mW at the supply voltage of 0.7 V. The tank impedance of the QILFD shows a dual resonance behavior, which leads to a dual-band locking range at a fixed bias condition. At the injection input power of 3 dBm, the low-band and high-band divide-by-2 locking ranges are from 6.90 to 8.56 GHz and 9.52 to 12.10 GHz, respectively. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26074

Dispersive magnetometry with a quantum limited SQUID parametric amplifier

There is currently fundamental and technological interest in measuring and manipulating nanoscale magnets, particularly in the quantum coherent regime. To observe the dynamics of such systems one requires a magnetometer with not only exceptional sensitivity but also high gain, wide bandwidth and low backaction. We demonstrate a dispersive magnetometer consisting of a two-junction SQUID in parallel with an integrated, lumped-element capacitor. Input flux signals are encoded as a phase modulation of the microwave drive tone applied to the magnetometer, resulting in a single quadrature voltage signal. For strong drive power, the nonlinearity of the resonator results in quantum limited, phase sensitive parametric amplification of this signal, which improves flux sensitvity at the expense of bandwidth. \ Depending on the drive parameters, the device performance ranges from an effective flux noise of 0.29\textbf{}$\mu\Phi_{0}$Hz$^{-\frac{1}{2}}$ and 20 MHz of signal bandwidth to a noise of 0.14 $\mu\Phi_{0}$Hz$^{-\frac{1}{2}}$ and a bandwidth of 0.6 MHz. These results are in excellent agreement with our theoretical model.

Quadrature Injection-Locked Frequency Dividers Using Dual-Resonance Resonator

This letter studies the property of a divide-by-2 quadrature injection-locked frequency divider (QILFD) with dual-resonance resonator. The QILFD consists of a transformer-coupled quadrature voltage controlled oscillator and two NMOS injectors. The proposed QILFD has been implemented with the TSMC 0.18 μm CMOS technology and the core power consumption is 3.4 mW at the supply voltage of 0.75 V. At the input power of 0 dBm, the low-band and high-band divide-by-2 operation ranges are respectively from 6.3 GHz to 8.2 GHz and 8.1 GHz to 10.3 GHz. The high-frequency band tuning range of free-running QILFD can be measured after the power-on, and the low-frequency band tuning range of free-running QILFD can be measured only after the low-frequency band injection signal is injected to the QILFD.

Assessment of effect of SSSC stabilizer in different control channels on damping inter-area oscillations

A static synchronous series compensator (SSSC) is one of the series flexible ac transmission system (FACTS) devices that injects a balanced three-phase voltage in quadrature with the transmission line current. There are two channels for controlling of phase and magnitude of the voltage. When the SSSC is used for damping of inter-area oscillations, a SSSC-based stabilizer can be included in both channels. In this paper, the best location and suitable input control signal for SSSC in order to enhance the damping of inter-area oscillations are selected by residue analysis. A method by quadratic mathematic programming has been presented to the design of the stabilizer. By this method, the effect of the stabilizer in both control channels of the SSSC on damping of inter-area oscillations has been assessed. By considering the gain of stabilizer as a criterion, obtained results from studying on a small and a large multi-machine power system show that the stabilizer in the phase control channel is more effective for damping inter-are oscillations.

A low-phase-noise CMOS quadrature VCO with PMOS back-gate coupling

A new PMOS backgate quadrature voltage controlled oscillator (QVCO) is designed and implemented using TSMC 0.18 μm 1P6M CMOS technology.The phase noise of the PMOS back-gate coupled QVCO operating at 1.5 V is measured to be −100 dBc/Hz and −125.08 dBc/Hz at 100 KHz and 1 MHz offset, respectively, for a low power consumption of 15 mW. The backgate QVCO demonstrates a wide frequency tuning range, a low phase noise, and a low power consumption. The corresponding figure-of-merit of the QVCO is −186 dBc/Hz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2682–2685, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25564

Resistorless dual-mode quadrature sinusoidal oscillator using a single active building block

This paper presents a new realization of resistorless mixed-mode (i.e. both voltage-mode and current-mode) quadrature sinusoidal oscillator using a new active building block (ABB) called the differential voltage current-controlled conveyor transconductance amplifier (DVCCCTA). The proposed oscillator circuit uses a single DVCCCTA, two grounded capacitors (GCs) and does not employ any external linear resistors. The tuning laws for the condition of oscillation (CO) and the frequency of oscillation (FO) are non-interactive; and controlled by separate bias currents. The circuit provides two explicit quadrature current outputs and two quadrature voltage outputs and thus can be classified as a mixed-mode quadrature oscillator. Another notable feature of the proposed circuit is that it can also be used as a biquadratic filter to realize low-pass and band-pass filtering functions simultaneously. Non-ideal analysis of the circuit is provided and PSpice simulation results have been included to verify the workability of the proposed circuit.

Realisations of single-resistance-controlled quadrature oscillators using a generalised current follower transconductance amplifier and a unity-gain voltage-follower

This article presents realisations of single-resistance-controlled-oscillators (SRCOs) using the recently proposed modern active building block (ABB), namely the generalised current follower transconductance amplifier (GCFTA) and unity-gain voltage-follower (UGVF). The SRCO is made using reduced number of components: one GCFTA and one UGVF as the ABBs, two resistors and two grounded capacitors. The circuit offers the advantage of non-interactive control of condition of oscillation and frequency of oscillation and enjoys low active and passive sensitivities. The circuit is also capable of providing two quadrature voltage outputs. PSPICE simulations have been carried out using the bipolar implementation of the circuits. The simulation results validate the theoretical analysis.

A LOW-VOLTAGE SCALABLE (1.8 V–0.75 V) CMOS FOLDED-CASCODE LC QUADRATURE VCO FOR RF RECEIVERS

This paper presents a scalable low voltage CMOS folded-cascode quadrature voltage controlled oscillator (QVCO) design for radio-frequency (RF) applications using the TSMC 0.18 μm 6M1P CMOS process technology. The simulated startup behavior of this proposed QVCO topology indicates that, the QVCO is free from bi-modal oscillation (frequency ambiguity). The QVCO provided extended voltage swing with the supply voltage scalable in the range of 1.8 V to 0.75 V. The QVCO operates in the frequency range of 4 GHz to 3 GHz (corresponding to supply voltage scaling in the range of 1.8 V to 0.75 V) with around 11.7% tuning range and low quadrature error. The QVCO had a power consumption under 10 mW within the specified supply voltage scaling range. Phase noise simulations using the Monte Carlo analysis provide an approximate phase noise estimate of ≈ -150 dBc/Hz at an offset of 600 KHz from the center frequency (@3.7 GHz) for operation using the 1.8 V supply voltage, using moderate inductor-Q values. Monte Carlo simulations were also carried out to determine the effects of the process, voltage and temperature variations.

Current-mode third-order quadrature oscillator

The author presents a current-mode current-controlled third-order quadrature oscillator circuit synthesised from a simple yet novel approach using basic bilinear blocks. The new circuit is more compact than the other third-order oscillators available in the literature and enjoys non-interactive frequency control, use of grounded capacitors and availability of both quadrature current and voltage outputs. PSPICE simulations are performed for the verification of the new circuit. Experimental evidence is further given for completeness sake. The new basic scheme is also useful for realising a quadrature oscillator using other active elements as well.

A 0.35 μm CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage–current feedback topology

This paper presents a new divide-by-2 quadrature injection-locked frequency divider (QILFD). The QILFD consists of a new transformer-coupled quadrature voltage controlled oscillator (QVCO) with the voltage–current feedback technique and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS QILFD has been implemented with the TSMC 0.35 μm CMOS technology and the core power consumption is 16.52 mW at the supply voltage of 2.2 V. The free-running frequency of the QILFD is tunable from 2.85 GHz to 3.07 GHz. At the input power of 0 dBm, the divide-by-2 operation range is from 5.48 GHz to 6.48 GHz. The phase deviation of free running quadrature output is about 0.53°.

Design of SIPC‐based complementary LC‐QVCO in 0.18‐μm CMOS technology for WiMAX application

PurposeThe purpose of this paper is to design and realize a low‐phase noise, high‐output power, and high‐tuning range, fully integrated source injection parallel coupled (SIPC)‐based inductor‐capacitor (LC)‐quadrature voltage controlled oscillator (QVCO) covering WiMAX frequency range in 0.18‐μm deep submicron CMOS technology.Design/methodology/approachA pMOS based‐SIPC LC‐QVCO topology is realized with the center frequency of 2.58 GHz. On chip spiral inductor is integrated with substantial quality factor, Q coupled with underlying pattern ground shield (PGS) shielding. An enhanced tuning range is achieved by integrating the diode connected MOS‐based varactors. The CMOS‐based autonomous SIPC LC‐QVCO circuit was characterized for its output phase noise, tuning range and power spectrum response via wafer probing, utilizing a signal source analyzer (Agilent E5052 A).FindingsA quadrature oscillator catering to the needs of local oscillator (LO) generation covering the frequency range of WiMAX is realized. The parallel coupled architecture adapts direct source coupling, bypassing the LC resonator tank and relaxes the close in phase noise up‐conversion. The design consumes 2.19 mm2 of active chip area and measures a phase noise of −114.34 dBc/Hz at 1 MHz of offset frequency with 2.67 GHz of output frequency at 0.9 V of input tuning voltage. The corresponding output power measures to be −10.1 dBm, well suited for mixer hard switching. The design is realized in one poly, six metal 0.18‐μm standard CMOS technology.Research limitations/implicationsOwing to convergence discrepancy in the analysis, a diode‐connected MOS varactor is adapted in contrary to the accumulation mode MOS varactors with superior tuning range.Practical implicationsThe designed SIPC LC‐QVCO is of need in the generation of low‐phase noise, highly matched quadrature LO generation covering the WiMAX frequency range. The adapted parallel coupling also relaxes the voltage headroom limitation.Originality/valueThis paper shows how a fully integrated CMOS‐based SIPC LC‐QVCO architecture is adapted with low‐output phase noise and low voltage headroom consumption covering the WiMAX frequency range.

FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters

This paper presents a single chip FPGA (Altera Cyclone II) controlled single phase inverter, programmed for the reduction of harmonics in the output voltage. Separate composite digital observers have been designed for extracting the fundamental and harmonic components of the voltage and the highly distorted current signals, particularly when the inverter supplies nonlinear loads. These observers have been embedded into the FPGA along with the controllers and I/O interfaces. The multiple observers yield very pure in-phase and quadrature voltage signals for use in the outer loop and similar signals for stabilizing the inner current loop. The Inverter could be modeled as a feed back control system with the fundamental component of the voltage as the desired output while the voltage harmonics take the role of noise creeping into the output. To obtain a very low total harmonic distortion in the voltage waveform, the well-known control strategy of using a very large feed back around the noise signal has been employed.

Resistor-less Mixed-mode Quadrature Sinusoidal Oscillator

The paper presents a realization of mixed-mode quadrature sinusoidal oscillator variants of current differencing transconductance amplifier. The proposed circuit is created using one modified current differencing transconductance amplifier (MCDTA), one current follower transconductance amplifier (CFTA) and two grounded capacitors. The circuit is resistor-less and the tuning laws for the condition of oscillation (CO) and the frequency of oscillation (FO) are independent. The circuit also provides two quadrature voltage outputs and two explicit quadrature current outputs. PSPICE simulation results have been included to verify the theoretical results.