Quadrature Voltage-controlled Oscillator Research Articles

Integer- and Fractional-Order VCO Using Non-Inertial Amplitude Stabilization and Modern Active Elements

This paper introduces design of the linearly tunable quadrature voltage-controlled oscillator (VCO) using modern off-the-shelf active elements suitable for the design of electronically adjustable applications. The simplified topology was achieved using non-inertial stabilization of amplitude. It allows targeting adjustability of the oscillation frequency only into lossless integrator part of the topology. This arrangement simplifies the design and the tenability also. Derived symbolical expressions indicate that gain adjustment of used amplifiers (that are still in single path) does not influence amplitude and phase shift ratio of generated waveforms, which is a beneficial feature. The performances of the circuit are tested experimentally in band of units of MHz and results confirmed expected behavior. Initial study of the oscillator with fractional-order capacitors is presented and discussed. Results are supported by laboratory measurements.

Analytical phase noise study of a back-gate coupled colpitts quadrature VCO

This paper presents a detailed study of phase noise of an LC Quadrature Voltage-Controlled Oscillator (QVCO). This QVCO is made of coupling two identical cross-connected Colpitts oscillators as core oscillators. MOSFETs are used as varactors, the substrates of which are used for coupling the two core Colpitts oscillators. Phase noise improvement resulted from substrate coupling is not only due to elimination of noise sources (as no extra passive or active coupling devices are used) but also due to lower effective thermal noise of the substrates. To verify this, a rigorous phase noise analysis of the circuit using the Linear Time Variant (LTV) model is performed for the 1/f2 region. It indicates that the improvement is not only due to lower thermal noise of the substrate, but also a better noise modulating factor (NMF). The proposed QVCO was designed and simulated in a 0.18 ​μm RF-CMOS Technology at frequency of 5.35 ​GHz with a power consumption of 8 ​mW, tuning range of 18% and phase noise of −142.8 ​dBc/Hz at 5 ​MHz frequency offset. The presented analysis indicates a phase noise of −143 ​dBc/Hz at an offset of 5 ​MHz, which shows a good agreement with the simulation. The difference between the simulated and calculated phase noise at high frequency offsets is less than 0.2 ​dB.

Ultra-wideband Quadrature LC-VCO using Capacitor-Bank and backgate topology with on-chip spirally stacked inductor in 0.13 ​μm RF-CMOS process covering S–C bands

Frequency tracking and synthesizer at the mm-wave range suffer an everlasting compromise between phase noise (PN) performance and frequency tuning range (FTR) irrespective of the topology adopted. This work proposes an Ultra-Wide Band, Quadrature Voltage Controlled Oscillator (QVCO) employing an on-chip inductor and 8-Bit Capacitor-Bank (Cap-Bank) in addition to the MOS-Varactors, to bring in the best compromise between above two said constraints. The additional efforts are kept generating Quadrature operation and keeping the power dissipation in an optimized range. It is shown that unlike conventional current reuse and wider MOS topology, the proposed Cap-Bank array with scaled transistor-based switches effectively widens the tuning operation with a remarkable FTR up to 85.7%, covering the most frequently used wireless standards IEEE-802.11 a/b/g of Bluetooth and Wi-Fi in S and C bands respectively. The design has been implemented with 0.13 ​μm RF-CMOS process in ADS (Keysight Technologies). The Back-Gate topology has been used with the cross-coupled differential structure which generates the quadrature phased signals well-shaped and with the least add on power dissipation. Use of a low-loss on-chip spirally stacked inductor, enhances the chip integrity, spectrum quality and improves Phase Noise performance, providing the best phase noise of −164 dBc/Hz at 1 ​MHz (near fmax) at a power dissipation of 12 ​mW from 1.2 ​V supply. The VCO gain achieved for the entire range of 2.4–6 ​GHz, varies largely from 1332 ​MHz/V (near fmax ​= ​6 ​GHz) to 42 ​MHz/V (near fmin ​= ​2.4 ​GHz) for the coarse tuning of Cap-Bank.

A comparative study between Class-C and Class-B quadrature voltage-controlled power oscillator for multi-standard applications

In this paper a 0.35 ​mW Class-C/B series coupling quadrature voltage-controlled power oscillator (S-QVCO) based on the coupling between two identical LC VCOs is presented. The S-QVCO is designed using a 130 ​nm CMOS technology and it is suitable for multi-standard applications. High quality factor inductor is designed using the two top metal layers to enhance the phase noise performance of the VCO, also an improved switching varactor is used to achieve dual bands. The proposed QVCO achieves tuning range of 28.2% from 2.3 to 3.07 ​GHz, and low phase noise of −119.2 dBc at a 1-MHz offset frequency from 2.7 ​GHz carrier. By biasing the proposed QVCO in class-C, the DC current is reduced to 0.35 ​mA compared to 1.48 ​mA in class-B from 1 ​V supply voltage. The minimum achieved Figure-of-Merit (FOM) equals −192 dBc/Hz and the maximum given output power is 6.5 dBm. The phase error between quadrature output signals is maximum of 0.25° . The occupied area of the proposed QVCO equals0.34mm2, while the total chip area including RF pads is1mm2.

300-GHz InP HBT Quadrature VCO With Integrated Mixer

A 300-GHz quadrature voltage-controlled oscillator (QVCO) integrated with a pair of mixers based on an InP heterojunction bipolar transistor (HBT) technology has been developed. A super-harmonic coupling technique was applied to generate the quadrature signal in the QVCO. The oscillation frequency tuning range is 24.8 GHz (from 286.1 to 310.9 GHz), and the frequency range maintaining the quadrature operation (within ±10°) is 4.8 GHz (297.2–302.0 GHz). The maximum output power of the QVCO was measured as 0.46 dBm at 286.3 GHz. The measured phase noise is −91.4 dBc/Hz with 10 MHz offset at 294.2 GHz. The integrated QVCO-mixer consumes a dc power of 167.5 mW.

Voltage-variable inductor based linear voltage controlled quadrature oscillator implementation

Voltage-variable inductor based linear voltage controlled quadrature oscillator implementation

A 37.5–45 GHz Superharmonic-Coupled QVCO With Tunable Phase Accuracy in 28 nm CMOS

This paper presents a new superharmonic coupling structure for millimeter-wave (mmW) quadrature voltage-controlled oscillators (QVCOs) with high phase accuracy and zero voltage headroom. The proposed coupling network can adjust the quadrature error with almost no phase noise penalty. A tail impedance theory for superharmonically coupled oscillators is introduced to analyze the locking mechanism, phase noise, phase accuracy, and phase tunability of the proposed superharmonic QVCO. For verification, a 40 GHz QVCO is fabricated in a 28 nm bulk CMOS process, which exhibits a phase noise of −94.32 dBc/Hz at 1 MHz offset and 0.18° quadrature error with 8.4 mW power consumption and 18.4% frequency tuning range.

K‐band low‐power dual‐hybrid‐coupling quadrature voltage‐controlled oscillator

A low-power and low phase noise quadrature voltage-controlled oscillator (QVCO) is presented for short range radar systems here. A dual-hybrid coupling (DHC) technique is adopted to increase the output voltage swing. The second harmonic filters are applied to eliminate the phase noise as well as to suppress the phase error. The proposed DHC-QVCO was implemented with a low cost standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) process technology. The oscillation frequency is operated between 19.8 and 21.5 GHz. The tuning range is 8.5%. The phase noise achieves −100.1 dBc/Hz at 1 MHz offset from a carrier frequency of 20.6 GHz. The phase error and gain error are 4.29° and 3.2 dBm, respectively. The core circuit consumes only 5.15 mW from a power supply of 1.5 V. The designed DHC-QVCO has demonstrated the advantages of low-power, low phase noise, and wide tuning range for K-band applications.

Low power quadrature voltage controlled oscillator

In this article, a low voltage low power quadrature voltage controlled oscillator (QVCO) coupled by four P&N transistors is presented. First, a novel negative resistance inductance capacitor (LC) oscillator is described, the N-metal oxide semiconductor (NMOS) and P-metal oxide semiconductor (PMOS) transistors are in series with the LC tank in the direct-current (DC) path, and they generate the required negative resistance to compensate the energy loss of the LC tank and maintain the steady oscillation of the oscillator. Then, based on two identical LC oscillators, four P&N transistors are used as coupling terminals to generate quadrature outputs. The proposed QVCO is designed and simulated with GlobalFoundries' 0.18 μm CMOS RF process. The Cadence IC design tools postlayout simulation results demonstrate that the oscillation frequency of the QVCO can be tuned from 2.0 to 5.6 GHz by adjusting the bias voltage, and the phase noise of the voltage controlled oscillator is −114 dBc/Hz at 1 MHz offset. Moreover, the proposed QVCO consumes only 2.31 mW from a 1.2 V supply voltage and it occupies a compact area of 0.45 mm2 including the bond pads.

A Direct Bulk Coupling PMOS Colpitts QVCO Using Capacitive-Feedback Structure

In this paper, a full PMOS Colpitts quadrature voltage-controlled oscillator (QVCO) topology, suitable for low supply voltage and low power dissipation, is presented. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed. Quadrature coupling is achieved by employing direct bulk coupling technique, leading to reduction in both power and chip area. The proposed QVCO covers a 5% tuning range between 2.325 GHz and 2.435 GHz, and the phase noise is [Formula: see text]128.2 dBc/Hz at 1-MHz offset from the 2.34-GHz carrier while consuming only 0.535 mW from 0.55-V supply voltage, yielding a figure-of-merit (FoM) of 198 dBc/Hz.

A 93.4–104.8-GHz 57-mW Fractional-${N}$ Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology

A fully integrated 93.4–104.8-GHz 57-mW fractional- ${N}$ cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional- ${N}$ PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm2. The measured phase noise of QVCO and PLL is −113.26 and −106.63 dBc/Hz at 10-MHz offset, respectively. The FOM and FOMT of the QVCO at 10-MHz offset are −178.4 and −180.0 dBc/Hz, respectively. The frequency resolution of the 100-GHz output is less than 3.6 kHz.

Comparative Studies of Transistors- and Capacitors-Coupled QVCOs

The comparative studies of realizing quadrature voltage-controlled oscillator (QVCO) with MOS transistors and capacitors are presented in this paper. The supply voltage, power consumption, chip area, phase accuracy, phase noise, starting time and frequency tuning range of the two kinds of QVCOs are compared. The two kinds of QVCOs are simulated with GlobalFoundries’ 0.18 μm CMOS RF process, and the Cadence IC Design Tools post-layout simulation results demonstrate that the MOS transistors-coupled QVCO has a low supply voltage, low power consumption and improved phase accuracy; the capacitors-coupled QVCO has low phase noise and short starting time; the chip area and other parameters of the two kinds of QVCOs are the same. The two kinds of QVCOs satisfy the average requirements of modern RF transceivers, so the MOS transistors-coupled QVCO is suitable for low-voltage, low-power-consumption and strict accurate phase requirement transceivers.

Systematic Analysis of Quadrature VCO With Capacitive Source Degeneration Coupling and Spontaneous Transconductance Matching Techniques

This brief proposes a quadrature voltage-controlled oscillator (QVCO) using capacitive source degeneration coupling (CSDC) and spontaneous transconductance matching (STM) techniques. Mismatch in QVCO structure results in serious phase and gain errors. Thus, a CSDC structure is used to overcome phase error, and an STM structure is adopted to reduce gain error. Moreover, a systematic analysis of QVCO on the proposed techniques is presented to design a remarkable phase error of less than 0.1°. Measurement results reveal that the proposed QVCO has a phase error of 0.07° at 2.45 GHz. The measured phase noise is −121 dBc/Hz at 1 MHz offset and consumes 3.81 mW under a 1.8V supply voltage, which achieve a figure of merit of −182.98. The tuning range should be between 2.303 GHz and 2.475 GHz to fit the requirement of IEEE 802.15.4.

A Modified High Phase Accuracy SIC-QVCO Using a Complementary-Injection Technique

This letter presents a complementary-injection-coupled technique to modify the conventional self-injection-coupled quadrature voltage-controlled oscillator (QVCO) topology. The proposed topology reduces the influence of dc offset problem at the source node of the coupling transistors that possibly makes the QVCO to fail and stop generating quadrature signals. Meanwhile, the modified coupling network provides an extra phase shift to resolve the bimodal oscillation. The QVCO is implemented in TSMC 0.18- $\mu \text{m}$ CMOS technology. The measured phase noise is −111 dBc/Hz at 1-MHz offset, and the phase errors are from 0.29° to 1.39°. The figures of merit (FoM, FoM $_{Q}$ ) are −178.2 and −228.4 dBc/Hz, respectively. The chip area is $1.12\times0.73$ mm $^{2}$ .

NanoCMOS optimized DVCC-based quadrature voltage controlled oscillator performances prediction through bisquare-weights method

This paper dealt with the prediction of optimized quadrature voltage controlled oscillator (QVCO) performances for the upcoming CMOS nanoprocess using the robust bisquare weights (BW) method. Using differential voltage current conveyor, the QVCO was optimized for low power consumption with TSMC 0.18 µm CMOS process under ± 0.9 V supply voltage and relying on the Heuristic method. To provide solutions to the nanoscale CMOS challenges, a synoptic of nanoCMOS circuit performances prediction including the BW method was proposed to predict the performances of the optimized QVCO circuit. Some predicted performances for 45–22 nm process nodes were obtained in order to solve design challenges generated by upcoming analog high frequency (HF) systems with severe requirements. The behaviour of the optimized QVCO performances with process scaling were detailed.

A Low-Power 0.6-V Quadrature VCO With a Coupling Current Reuse Technique

A novel quadrature voltage-controlled oscillator (QVCO) featuring low power consumption is proposed in this brief. By utilizing the coupling current reuse technique, the coupling current of one core is shared as a source to bias the quadrature coupling device in the other core. Thus, the coupling current consumption is eliminated. Moreover, the injected tank current is reshaped to reduce noise injection and increase efficiency. The coupling current reuse technique allows the proposed QVCO to achieve at least 50% power consumption decreasing compared to previous LC-QVCOs without sacrifices of phase noise and swing. In addition, the quadrature coupling topology is reused as an oscillation detector for dynamic bias control to further decrease power consumption of oscillation cores. A proto-type of the proposed QVCO is designed and fabricated in a 40-nm CMOS process. Measurement results indicate that the QVCO achieves a phase noise of −118.6dBc/Hz@1 MHz at the carrier of 1.575 GHz. The power consumption of the proposed QVCO is only 1.32 mW under the supply voltage of 0.6 V.

A low phase noise quadrature VCO using superharmonic injection, current reuse, and negative resistance techniques in CMOS technology

In this article, a low phase noise quadrature VCO (QVCO) is proposed, which uses superharmonic injection and current reuse techniques to reduce phase-noise and power consumption. The LC tank circuit quality factor is improved, using a negative resistance. PMOS transistors have also been used instead of NMOS transistors. As a result of these modifications, further phase noise reduction is achieved. The QVCO consists of a VCO operating at 2ω0 (twice the operating frequency) injecting its output signal into the common source nodes of two other oscillators operating at ω0. Using this superharmonic injection technique, in addition to phase noise reduction, the chance of injection pulling caused by powerful PA signals is reduced. Also, the current reuse technique automatically adapts its voltage to the requirement of the supplied stages, therefore, it is not limiting the VCO output swing. Designed for the 900 MHz band and simulated in a 0.18 µm CMOS technology with 1.8 V power supply, the circuit achieves a phase noise of − 141.5 dBc/Hz at 1 MHz offset frequency, while consuming 12.8 mW power. The proposed circuit is compared with several re-simulated previously published work. The comparison shows 17.5 dB reduction in phase noise compared to conventional P-QVCO, while consuming the same amount of power.

Low-power Gm-boosted complementary Colpitts LC-VCO/QVCO

In this work, a new differential topology of Colpitts VCO with an enhanced transconductance is presented. The proposed circuit is consisted of an NMOS and a PMOS differential Colpitts cores configured as complementary, and also an LC resonator. The VCO is designed to oscillate at 5 GHz which consumes 1.11 VA from 1.4 V supply voltage. In addition, a modified version of the proposed VCO is designed for lower power applications. This circuit employs new positive feedbacks to enhance the VCO’s transconductance and reduce the supply voltage. The modified VCO operates with 1.1 V power supply while dissipating 1 mW. To investigate the performance of the proposed circuits, the transconductance of them are theoretically analyzed. Also, two new quadrature VCOs (QVCOs) are presented which are realized by two identical latter proposed Colpitts VCOs. A linear analysis is presented to confirm that the first oscillator can generate outputs with 90° phase differences. The proposed circuits are designed in 0.18-μm RF-CMOS technology. Finally, prototype circuits of the proposed VCOs are fabricated to validate the theoretical results. The measurement results are summarized to demonstrate the main features of the proposed oscillators.

A low phase noise super–harmonic coupling quadrature VCO using an additional double frequency oscillator

In this paper, using an additional oscillator that operates at twice the main output frequency, super–harmonic coupling is created between two LC cross–coupled oscillators. The additional oscillator output signals are injected into the two main oscillators in a special way, such that in addition to forcing those oscillators to work in quadrature mode, a tail current shaping technique is performed on them, through the same circuit path. As a result, the main oscillators output phase noise is reduced. The second harmonic signals with the help of two additional NMOS transistors shape the gate voltages and consequently the drain current of the tail transistors. The quadrature mode operation of the proposed circuit is mathematically proved and the intrinsic tail current shaping behavior of it is analyzed. The proposed QVCO is designed in a 0.18 μm CMOS technology with a supply voltage of 1.8 V and a total power consumption of 4.4 mW at 2 GHz center frequency with 5.5% tuning rage. Simulation results confirm the proposed quadrature mode operation. It also shows the phase noise of −128.1 dBc/Hz for the proposed QVCO at 1 MHz offset and 1.92 GHz carrier, which is 9.3 dB better than that of the conventional Parallel (P)–QVCO. The maximum phase error for 0.5% I and Q tank capacitor mismatch is 1.47°.

Bandwidth-enhanced differential VCO and varactor-coupled quadrature VCO for mmWave applications

This paper presents a bandwidth-enhanced differential LC-Voltage Controlled Oscillator (LC-VCO) and varactor-coupled Quadrature VCO (QVCO) designed and simulated in high-performance SiGe HBTs of the GlobalFoundries (GFs) 130 nm SiGe BiCMOS8HP process for mmWave applications. Using the proposed varactor circuit, the designed VCO is operated in wideband and also the two-identical free-running differential VCOs (DVCOs) are coupled through the proposed varactor to oscillate in quadrature. The device sizes in the coupling network are properly set to achieve low I/Q errors. In addition, all the VCOs are designed in class-C to further improve their performances both in term of low power and low phase noise. The post-simulation results show that the differential oscillator is tunable from 20.3- to 31.3-GHz as the tuning voltage is varied from 0 to 1.2 V, while consuming only 10 mA from 1.2 V supply, presenting the best state-of-the-art figure-of-merit (FoMT) of −188 dBc/Hz. Similarly, the QVCO can cover 40.2% oscillation bandwidth around 25.5 GHz oscillating frequency which is significantly wider than other state-of-the-art VCOs operating at comparable frequencies.