Quadrature Voltage-controlled Oscillator Research Articles

Bottom-series coupled quadrature VCO using the inductive gate voltage boosting technique

This article presents a new low-voltage bottom-series coupled quadrature voltage-controlled oscillator (QVCO), which consists of two n-core cross-coupled VCOs with the bottom-series coupling transistors. The low-voltage operation is obtained via an inductive gate voltage boosting technique. The proposed CMOS QVCO has been implemented with the TSMC 0.18 µm CMOS technology and the die area is 0.897 × 0.767 mm2. At the supply voltage of 0.7 V, the total power consumption is 1.5 mW. The free-running frequency of the QVCO is tuneable from 3.77 to 4.12 GHz as the tuning voltage is varied from 0.0 to 0.7 V. The measured phase noise at 1 MHz frequency offset is −123.35 dBc/Hz at the oscillation frequency of 4.12 GHz and the figure of merit of the proposed QVCO is −193.5 dBc/Hz.

A CMOS quadrature VCO implemented with direct capacitor injection‐locking

ABSTRACTThis article presents a new quadrature voltage‐controlled oscillator (QVCO). The LC‐tank QVCO consists of two first‐harmonic injection‐locked oscillators (ILOs). The outputs of one ILO are injected to the common nodes of capacitors on the other ILO and vice versa so as to force the two ILOs operate in quadrature. At the supply voltage of 1.1 V, the total power consumption is 5.94 mW. The free‐running frequency tuning range is 11.5%, tunable from 6.56 to 7.36 GHz as the tuning voltage is varied from 0.0 to 2 V. The QVCO has been implemented with the TSMC 0.18‐μm CMOS technology and the die area is 0.504 × 0.803 mm2. The measured phase noise at 1‐MHz offset is −123.01 dBc/Hz at the oscillation frequency of 7.34 GHz and the figure of merit of the proposed QVCO is about −192.5 dBc/Hz. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2528–2531, 2013

A 325 GHz Quadrature Voltage Controlled Oscillator With Superharmonic-Coupling

We present a 325 GHz quadrature voltage controlled oscillator (QVCO) using 0.25 μm InP HBT technology and superharmonic coupling of two differential Colpitts VCOs. The individual VCOs exhibit about -5-dBm single-ended output power and 10 GHz frequency tuning range. The quadrature oscillation is successfully demonstrated with dc power consumption of 92.4 mW and phase imbalance less than ±12° at around 325 GHz.

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

A dual-band quadrature VCO with gain proportional to oscillation frequency

This paper presents a novel dual-band quadrature voltage controlled oscillator (VCO) with the gain proportional to the oscillation frequency. Frequency synthesizers with this VCO can reduce the bandwidth fluctuation over all the frequency ranges without compensation or calibration. Besides the original switched capacitor array, an extra switched varactor array is adopted for the implementation of the proposed VCO. The tuning technique of changing the values of the capacitor and varactor at the same ratio is also derived. For verification purposes, a 2.5 G/3.5 G dual-band quadrature VCO is fabricated in a 0.13 μm CMOS process for WiMAX applications. Measurement results show that the VCO gain is closely proportional to the oscillation frequency with ±16% variation over the entire frequency range. The phase noise is −138.15 dBc/Hz at 10 MHz from the 2.5 GHz carrier and −137.44 dBc/Hz at 10 MHz from the 3.5 GHz carrier.

A 5-GHz CMOS LC Quadrature VCO With Dynamic Current-Clipping Coupling to Improve Phase Noise and Phase Accuracy

This paper presents a quadrature voltage-controlled oscillator (QVCO) employing a proposed dynamic current-clipping coupling technique to provide around 90° phase shift in the coupling paths. The phase shift given by the coupling network not only improves the phase noise, but also desensitizes the phase error to component mismatches in the QVCO. The coupling network furthermore reduces the noise injected into the LC tank at the most vulnerable time (zero crossing points). The proposed current-clipping coupling allows the use of a strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1-MHz offset from a 5-GHz carrier. The QVCO consumes 4.2 mW from a 1-V power supply, resulting in an outstanding figure of merit of 189 dBc/Hz.

A source degenerated LC quadrature VCO (SD-QVCO) using 0.18-μm SiGe BiCMOS

This letter presents a fully integrated BiCMOS quadrature voltage-controlled oscillator (QVCO). The QVCO consists of two nMOSFET cross-coupled oscillator stacked in series with source degenerated HBT transistors. SiGe HBT introduces low flicker noise compared to CMOS devices. To generate quadrature phase signals with strong coupling strength, the proposed design uses two MOS-coupled LC-tank cores instead of passive device-coupled cores. This source degeneration topology can improve the phase noise performance of the QVCO as compared to the sub-VCO. The proposed QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M BiCMOS process, can generate quadrature signals in the frequency range of 4.52–5.05 GHz with core power consumption of 5.76 mW at the dc bias of 1.8 V. At 4.53 GHz, phase noise at 1 MHz offset is −124.52 dBc/Hz. The die area of the fabricated prototype is 0.453 × 0.898 mm2.

A CMOS Transformer-Based Current Reused SSBM and QVCO for UWB Application

This paper presents the design of a low-voltage current-reused single-sideband mixer (SSBM) and quadrature voltage-controlled oscillator (QVCO) for Mode-1 multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer application. The proposed architecture is a low-voltage and low-power solution by stacking the SSBM on top of a pMOS parallel QVCO. For low-voltage operation, two symmetric transformers are used to perform quadrature oscillation and signal coupling. In addition, source degeneration capacitors are introduced to eliminate bimodal oscillation in QVCO and fix the phase sequence of the quadrature signal. For experimental demonstration, the proposed circuit was fabricated in a 0.18- $\mu{\hbox {m}}$ CMOS technology. The prototype occupies a core area of 0.8 $ {\hbox {mm}}^{2}$ and consumes about 11 mA from a 1.6-V power supply. Measurement results show that the image spurious rejection is over 43 dBc and the output phase noise of the SSBM is better than ${-}{\hbox{111.4 dBc/Hz}}$ at 1-MHz offset from carrier (3.432 GHz).

65-nm CMOS Dual-Gate Device for Ka-Band Broadband Low-Noise Amplifier and High-Accuracy Quadrature Voltage-Controlled Oscillator

Design and analysis of a two-stage low-noise amplifier (LNA) and a bottom-series coupled quadrature voltage-controlled oscillator (QVCO) using a 65-nm CMOS dual-gate device are present in this paper. By using the proposed dual-gate device, the parasitic capacitance and the effective substrate resistance can be reduced. Moreover, the 3-dB cutoff frequency can be extended due to the reduction of the Miller effect. The bandwidth of the dual-gate LNA is investigated to compare with the conventional cascode configuration. Besides, the operation principle of the quadrature signal generation using the dual-gate device is also presented for the QVCO design. The two-stage dual-gate LNA demonstrates a flat 3-dB bandwidth of 7.3 GHz from 19.4 to 26.7 GHz and a maximum gain of 18.9 dB. At 24 GHz, the measured minimum noise figure is 4.7 dB, and the measured output third-order intercept point <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$({\rm OIP}_{3})$</tex></formula> is 11 dBm. The dual-gate QVCO exhibits an oscillation frequency of up to 25.3 GHz, a phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 109 dBc/Hz at 1-MHz offset frequency, an amplitude error of 0.16 dB, and a phase error of 0.8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}$</tex></formula> . The proposed dual-gate CMOS device is very suitable for the linear and nonlinear circuit designs above 20 GHz, especially for millimeter-wave applications due to its high speed and compact area.

An Nmos Cross-Coupled Quadrature Vco using Coupling Common-Gate Pmosfets

This letter presents a fully integrated cross-coupled quadrature voltage-controlled oscillator (QVCO) using common-gate transistor instead of common-source transistor as a coupling device. The prototype wide-tuning X-band QVCO in 0.18-μm CMOS process is proposed to generate four output phases and consists of two n-core cross-coupled VCOs and four pMOS coupling devices. The proposed QVCO oscillates from 8.52 to 10.56 GHz and the power consumption is 9.76 mW at 0.8 V supply voltage. The measured phase noise is −118.88 dBc/Hz at 1-MHz offset frequency from the carrier frequency 9.86 GHz. The QVCO occupies a chip area of 0.623 × 1.197 mm2 and provides a figure of merit of −188.86 dBc/Hz. The figure of merit including tuning range, FOMT, of this QVCO is −195.30 dBc/Hz. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1705–1708, 2013

A 1.1-mW-RX ${-}{\hbox{81.4}}$-dBm Sensitivity CMOS Transceiver for Bluetooth Low Energy

This paper presents a fully integrated low-power 130-nm CMOS transceiver tailored to the Bluetooth low energy (BLE) standard. The receiver employs a passive front-end zero-IF architecture, which is directly driven by a quadrature voltage-controlled oscillator (QVCO) without any buffering stage. The QVCO, embedded in a fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked loop (PLL), employs a passive <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> network to cancel the parasitic magnetic coupling between the two cores so as to keep the quadrature phase error below 1.5°. The PLL exhibits a high loop bandwidth of 1 MHz to sufficiently reduce the frequency pulling effects due to close-by interferers. The transmitter uses a direct-modulation Gaussian frequency-shift keying scheme in which small PMOS-based cells modulate the output signal of one of the cores of the QVCO. In the baseband section, the transceiver employs a 4-bit phase-domain ADC based on novel linear-combiner topology to generate the required phase rotations. The proposed combiner operates in current domain and does not employ resistors, leading to a power- and area-efficient demodulator implementation. The complete receiver achieves a sensitivity of - 81.4 dBm and fulfills the BLE requirements on interference blocking. It consumes 1.1 mW from a 1.0-V supply and has a similar power efficiency as recent super-regenerative receivers that are much more susceptible to interferers. The transmitter delivers 1.6-dBm output power to a differential 100 Ω and consumes 5.9 mW, which implies a total efficiency of 24.5%.

A Current-Switching and $g _{m}$-Enhanced Colpitts Quadrature VCO

This letter presents the design and analysis for a low-phase-noise and low-power Colpitts quadrature voltage-controlled oscillator (QVCO). The Colpitts QVCO employs current switching to lower the phase noise, gm enhancement to improve the startup condition in the oscillator core, and device reuse to realize anti-phase injection locking for QVCO operation. The proposed Colpitts QVCO has superior phase noise than cross-coupled LC tank VCO and outperforms conventional QVCO in phase noise, quadrature phase accuracy, and tuning range. The fabricated 0.18 μm CMOS Colpitts QVCO draws 500 μA from a 1.5 V power supply and exhibits a phase noise of -118 dBc/Hz at 1 MHz offset and a quadrature phase error of 0.3° at the center frequency of 488 MHz.

A Back-Gate Coupling Quadrature Voltage-Control Oscillator Embedded With Self Body-Bias Schema

A quadrature voltage-controlled oscillator was designed with back-gate coupling and embedded self body-biasing and implemented with the TSMC 0.18 μm 1P6M CMOS technology. Without using any extra negative bias-pin in the current-reuse structure, this embedded body-bias schema makes the switching transistors become forward body-biased in the duration of turn-on. It is not only beneficial for low-voltage operation, but also achieves a high oscillating output power (-2.5 dBm) with less supply power (2.5 mW). The percentage of frequency tuning range is 17.5% (from 4.60 to 5.48 GHz). The phase noise is -114 dBc/Hz at 1-MHz offset from the carrier frequency of 5.48 GHz.

A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling

A new low-phase noise low-power quadrature voltage-controlled oscillator (QVCO) using differential Colpitts oscillator is presented. The proposed QVCO is composed of two identical current-switching differential Colpitts VCOs in which the first core VCO is coupled to the second in an in-phase manner, and the second core VCO is coupled to the first in an anti-phase manner. To couple the two core VCOs, the substrates of the cross-connected transistors as well as the substrates of MOS varactors are used; alleviating the need for any extra elements for coupling, which could add noise and increase power dissipation. A linear (sinusoidal) analysis is presented that confirms that the proposed circuit generates quadrature waveforms. The proposed coupling technique can be generalized to N differential Colpitts VCOs for multiphase signals generation.

A fully-integrated CMOS quadrature VCO implemented with balanced VCOs

A new CMOS quadrature voltage-controlled oscillator (QVCO) is proposed. The LC-tank QVCO consists of two balanced complementary Colpitts VCOs with differential outputs. The tail inductor output of the first balanced VCO is injected to the gate of the tail transistor in the second balanced VCO and vice versa to ensure the two balanced VCOs operate in quadrature. At the supply voltage of 1.2 V, the total power consumption is 4.32 mW. The free-running frequency tuning range is 13.4%, tunable from 5.92 to 6.77 GHz as the tuning voltage is varied from 0 to 2 V. The QVCO has been implemented with the TSMC 0.18 μm CMOS technology and the die area is 0.843 × 1.024 mm2. The measured phase noise at 1 MHz offset is −121.67 dBc/Hz at the oscillation frequency of 6.74 GHz and the figure of merit of the proposed QVCO is about −191.89 dBc/Hz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:700–703, 2013; View this article online at wileyonlinelibrary.com. DOI: 10.1002/mop.27433

A Novel, Low-Voltage, Current Reused, Quadrature VCO and Divide-by-4 Frequency Divider Circuit

A low-voltage, current-reused, quadrature voltage controlled oscillator (QVCO) and divide-by-4 frequency divider (FD4) architecture is presented for the first time. The proposed architecture features compact and low voltage operation by the proper stacking of a ring-type injection locked FD4 and a back-gate coupled QVCO. This design lowers the power consumption and eliminates the need of high frequency divider as well as buffering stage. The circuit has been implemented in 0.18-μm triple-well CMOS process. Experimental results show a phase noise level of -114.1 dBc/Hz at 1 MHz offset from carrier (2.2 GHz). This chip occupies a core area of 0.9×0.35 mm2 and consumes 2.7 mA from a 1.3 V power supply.

A 0.4–6-GHz Frequency Synthesizer Using Dual-Mode VCO for Software-Defined Radio

This paper presents a dual-mode voltage-controlled oscillator (DMVCO) and a DMVCO-based wideband frequency synthesizer for software-defined radio applications. The DMVCO allows the synthesizer to leverage single-sideband (SSB) mixing, a power efficient approach, for high-frequency local oscillator (LO) signal generation, without the need of poly-phase filter or quadrature voltage-controlled oscillator (QVCO). When compared to the QVCO approach, the DMVCO solution allows the synthesizer to provide continuous LO signals without frequency gaps. The synthesizer is implemented in a 0.13-μm CMOS technology, occupying an active area of 2.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consuming 34-77 mW of power. It provides in-phase and quadrature-phase LO signals over the frequency bands of 0.4-3- and 5-6 GHz and differential LO signals from 0.4 to 6 GHz, supporting major wireless standards including DVB-T, GSM, WCDMA, TD-SCDMA, WLAN802.11 a/b/g, and Bluetooth. The measured phase noises are -135 and -124 dBc/Hz at 3-MHz offset under 1.8- and 5.15-GHz carriers, respectively. The measured spurious tones are less than - 42 dBc at the SSB mixer output.

CMOS quadrature VCO using a passive coupling device

This article presents a new fully-integrated quadrature voltage-controlled oscillator (QVCO), which consists of two differential VCOs coupled via an inductor-ring. The proposed CMOS QVCO has been implemented with the TSMC 0.18-μm CMOS technology and the die area is 0.693 × 0.976 mm2. At the supply voltage of 0.7 V, the total power consumption is 2.58 mW. The free-running frequency of the QVCO is tunable from 5.15 to 5.55 GHz as the tuning voltage is varied from 0 to 0.7 V. The measured phase noise at 1 MHz frequency offset is −120.88 dBc/Hz at the oscillation frequency of 5.28 GHz and the figure of merit of the proposed QVCO is −191.21 dBc/Hz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:310–313, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27283

Low-phase-noise 0.63-V, 1.7-mW, 11.55-GHz quadrature voltage controlled oscillator with intrinsic-tuned technique in 0.18-μm complimentary metal oxide semi-conductor

A low-power and low-phase-noise 11.55-GHz quadrature voltage-controlled oscillator (QVCO) using intrinsic-tuned technique is demonstrated in a standard 0.18-µm complimentary metal oxide semi-conductor (CMOS) technology. Intrinsic-tuned technique means the intrinsic junction capacitances at the drain terminals of the cross-coupled transistors are regarded as varactors, so no extra low-Q accumulation-mode MOS varactors are needed. This in turn results in a reduction of power consumption, a minimisation of parasitic capacitance effect (i.e. an increase of the operation frequency) and an improvement of phase noise. The QVCO core draws 2.7 mA current from a 0.63 V power supply, that is, it only consumes 1.7 mW. The QVCO achieves a tuning range of 3.9% (11.11–11.55 GHz) and a low phase noise of −114.7 dBc/Hz at 1 MHz offset from 11.55 GHz. The corresponding figure-of-merit is −193.6 dBc/Hz, one of the best results ever reported for an X-band CMOS QVCO/VCO. The core circuit occupies a chip area of only 0.64×0.58 mm2, that is, 0.37 mm2.

Pulse-Biased Low-Power Low-Phase-Noise UHF LC-QVCO for 866 MHz RFID Front-End

This paper discusses an 866-MHz UHF quadrature voltage-controlled oscillator (QVCO) for RFID front-end. The VCO achieved an improved phase noise performance of -130 dBc/Hz at a carrier-offset of 1 MHz using an improved architecture employing pulsed self-biasing. It was fabricated using the IBM 130-nm CMOS process with the core VCO occupying around 0.36 mm2 die area. The loading effect of finite gds for nanometric CMOS design was also considered. The VCO achieved 8% tuning range with very low quadrature error. It was tested using a power supply in the range of 0.6-1 V, drawing a maximum of 2.5 mW. In addition, it achieved a figure of merit of -185 dBc/Hz.