Quadrature Signals Research Articles

A new tail-switching superharmonic multiphase LC-VCO

PurposeMultiphase and quadrature voltage-controlled oscillators (QVCOs) play key roles in modern communication systems and their phase noise performance affects the performance of the overall system. Different studies are devoted to efficient quadrature signals generation. This paper aims to present a new low-phase noise superharmonic injection-locked QVCO.Design/methodology/approachThe proposed QVCO is comprised of two identical inductor-capacitor circuit (LC)-voltage-controlled oscillators (VCOs) in which second harmonics, with 180° phase shift, are injected from one core VCO to the gate of tail current source of the other VCO via a coupling capacitor. Using second harmonics with high amplitude will switch the tail from the inversion to the accumulation, and therefore, flicker noise is reduced. Also, because of the use of lossless and noiseless coupling elements, that is, coupling capacitors, and also because of the existence of an inherent high-pass filter, the proposed LC-QVCO has a good phase noise performance.FindingsThe introduced technique is designed and simulated in a commercial 0.18 µm radio frequency complementary metal oxide semiconductor (RF-CMOS) technology and 10 dB improvement of close-in phase noise is achieved (compared to the conventional method). Simulation results show that the phase noise of the proposed QVCO is −130.3 dBc/Hz at 3 MHz offset from 5.76 GHz center frequency, while the total direct current (DC) current drawn from a 0.9-V power supply is 4.25 mA (figure of merit = −190.2 dBc). Monte Carlo simulation results show that the figure of merit of the circuit has a Gaussian distribution with mean value and standard deviation of −189.97 dBc and 0.183, respectively.Originality/valueThis technique provides a new simple but efficient superharmonic coupling and noise shaping method that reduces close-in phase noise of superharmonic multiphase VCOs by switching of tail transistors with 2 ω0 (second harmonic of oscillation frequency). No extra devices such as area-consuming transformer or additional power-hungry oscillator are used for coupling.

An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer

A fully integrated energy-efficient 10-Gb/s millimeter-wave transceiver with direct-modulation digital transmitter (TX) and I/ Q phase-coupled frequency synthesizer in 65 nm CMOS is presented. The transceiver consists of a direct-conversion receiver (RX), a digital TX with on-chip QPSK modulation, and a quadrature local-oscillation (LO) generation network with a 20-GHz phase-locked loop (PLL) frequency synthesizer. A T/R switch is integrated to interface with an E-shaped patch antenna. The QPSK modulation is directly realized in the I/ Q digital power amplifier (DPA), which simplifies the TX complexity and reduces the power consumption. A 20-GHz sub-sampling PLL (SSPLL) and a quadrature phased-coupled injection-locked oscillator (QILO) are integrated on-chip to generate 60-GHz quadrature LO signals. The QILO utilizes in-phase coupling technique to improve the LO I/ Q matching and phase noise performance. The RX achieves 7.1-dB noise figure (NF) and 25- to 47-dB dynamic gain range. The LO phase noise measured at the TX output is -115.6 dBc/Hz at 10 MHz offset from 60 GHz carrier. The measured error vector magnitude (EVM) of the TX is -23.9 dB for 10-Gb/s QPSK signals at 7-dBm output power. The EVM of the over-the-air (OTA) modulation-demodulation system is -13.8 dB for 10-Gb/s QPSK signals. The transceiver achieves the 10-Gb/s data rate while consuming 340.4 mW. The energy efficiency is 34 pJ/bit. This work demonstrates the fully functional wireless link based on the proposed mm-wave transceiver, which highlights the possibility of energy-efficient solution for future high throughputs mm-wave wireless systems.

A Fabry–Perot Interferometer-Based Fiber Optic Dynamic Displacement Sensor With an Analog in-Phase/Quadrature Generator

In this paper, the design details of a low-cost and high resolution Fiber Optic Dynamic Displacement sensor are discussed. The sensor is designed based on the principle of extrinsic Fiber Optic Fabry-Perot Interferometer (FPI). Higher sensitivity is achieved by using a double pass sensor head configuration. To resolve direction ambiguity, quadrature signals are generated by employing Phase Generated Carrier (PGC) demodulation technique. An Analog In-phase/Quadrature phase (I/Q) generator is designed to perform light intensity compensation, carrier mixing, and filtering operations to obtain the quadrature signals. Arctangent algorithm and phase unwrapping algorithms are used to obtain dynamic displacement from the quadrature signals. The sensor is demonstrated to measure non-contact dynamic displacement at a working distance of 5 cm with an amplitude resolution of 12 nm, a precision of 1.4 nm, and a standard deviation of 2%. The sensor is also able to measure multi-frequency dynamic displacements generated by piezo actuators. Potential applications of the sensor include condition monitoring and predictive maintenance in industries.

Model predictive direct power control for modular multilevel converter under unbalanced conditions with power compensation and circulating current reduction

In this paper, a model predictive direct power control (MP-DPC) with power compensation and circulating current reduction is proposed for modular multilevel converter under unbalanced grid conditions. The main objectives of this paper are to achieve the circulating currents reduction and the power ripples elimination under unbalanced grid-side voltage conditions. In order to realize the aforementioned objectives, a triple-stage MP-DPC method based on a decoupled mathematical model of circulating current and DC-link current components is presented, which results in the elimination of weighting factors. Meanwhile, a power compensation term is embedded in the proposed design so as to eliminate the power ripples. In this sense, the power compensation terms are expressed by grid voltages and their quadrature signals without the complex positive/negative sequences extraction of grid voltage/currents and phase-locked loop. The proposed methodology can not only relieve the effect of circulating currents but also eliminate the active and reactive power ripples while remaining computationally feasible under unbalanced grid conditions. Additionally, a reduced switching frequency approach is introduced to decrease the power loss. Finally, the effectiveness of the proposed MP-DPC method is validated by both simulation and experimental results.

Measuring complex field waveforms of quadrature amplitude modulation optical signals using a spectrally slicing-and-synthesizing coherent optical spectrum analyzer.

We propose a spectrally slicing-and-synthesizing coherent optical spectrum analyzer to measure complex field waveforms of quadrature amplitude modulation (QAM) optical signals with ultralong periods. The optical spectrum of a measured optical signal is divided into multiple narrowband spectral components, called slices. The slices are sequentially measured using low-speed coherent detection. After phase noise suppression and frequency fluctuation compensation on each slice, the measured slices are synthesized to recover the original signal spectrum. Our numerical and experimental results confirm that the proposed method can overcome the limitation of the measurement bandwidth because the signal spectrum can synthesize more than 100 slices. We experimentally demonstrate complex field measurements of 16QAM optical signals. Our method can measure high-speed optical complex field waveforms with no bandwidth limitation.

Synchronous reference frame single‐phase phase‐locked loop (PLL) algorithm based on half‐cycle DFT

In single-phase power and energy applications, sliding discrete Fourier transform (SDFT) filter based quadrature signal generation is a well-known tool for designing advanced phase-locked loops (PLLs), particularly for applications where high disturbance rejection ability is demanded. The SDFT-based PLL, nevertheless, has a limited ability in achieving fast response (a response time more than one cycle of the nominal frequency). To deal with this problem, a synchronous reference frame PLL based on half-cycle DFT (HCDFT) is proposed, enabling a fast and accurate synchronisation even in distorted grid. In this study, the fundamental voltage of the PLL input signal is obtained by a HCDFT filter. Then, phase, frequency and amplitude can be detected by the improved synchronous reference frame phase-locked loop (SRF-PLL). Besides, in order to solve the phase error when the frequency changes, a phase compensator is used. The HCDFT-based SRF-PLL method proposed in this study is compared, through experimental results, with a number of conventional methods, showing that the phase can be estimated under grid voltage disturbances accurately and quickly, which verifies the effectiveness and superiority of the proposed algorithm.

I/Q Balance-Enhanced Wideband Receiver Front-End for 2G/3G/4G/5G NR Cellular Applications

In this paper, an in-phase (I) and quadrature-phase (Q) balance-enhanced wideband receiver RF front-end is proposed using a quadrature sampling passive mixer configuration, which can be applicable to 2G/3G/4G/5G new radio (NR) applications. Compensating mixer switches are additionally utilized in parallel with main mixer switches in a quadrature mixer for quadrature downconversion. As a consequence, gain and phase errors from the mixer can be mutually compensated at the mixer output, and I/Q imbalance characteristics are significantly improved without an extra calibration process. For the verification of I/Q balancing improvement, the receiver front-end is implemented, which consists of a wideband low noise transconductance amplifier, a double-balanced quadrature sampling passive mixer, transimpedance amplifiers, and quadrature local oscillator signal circuitry. The demonstrated design is fabricated in a 65-nm CMOS process and mainly characterized in long-term evolution (LTE) frequency bands. The implemented design achieves an error-vector magnitude of less than 2% with conversion gains and noise figures of more than 41 dB and less than 4.7 dB for all frequency bands, respectively. Moreover, the design attains in-band and out-of-band IIP3s of higher than −12 dBm and −2.7 dBm for LTE frequency division duplexing test conditions, respectively. The active die area of the implemented receiver front-end is 0.72 mm2. It draws a bias current of 18.2 mA from a nominal supply voltage of 1.2 V.

Two-Sample PLL With Harmonic Filtering Capability Applicable to Single-Phase Grid-Connected Converters

The two-sample phase locked loop (2S PLL) in single-phase digitally controlled grid-connected power converters provide synchronization with a minimal computational burden. However, the distortion of the grid voltage deteriorates the performance of the 2S quadrature signal generator. To solve this issue, this article introduces a harmonic filtering (HF) structure based on observers of the input voltage for the fundamental and selected harmonics. The stability and sensitivity of the 2S PLL with HF is analyzed. In comparison with second-order generalized integrator (SOGI)-based HF, the observers provide a narrower bandpass, and the subsequent deterioration of the response time is compensated by adapting the filter gains dynamically. The results obtained, both in simulation and experimentally, validate the proposal and compare its performance with other widely adopted PLLs providing harmonic rejection capability. The computational burden is analyzed and in the case of the proposals depends on the number of observers and the use or not of the adaptive strategy based on steepest descent.

The Generalization of Orthogonal Frequency Division Multiplexing With Subcarrier Power Modulation to Quadrature Signal Constellations

The Generalization of Orthogonal Frequency Division Multiplexing With Subcarrier Power Modulation to Quadrature Signal Constellations

Signal Converter with Three-Phase and Quadrature Outputs for Driving Synchros and Resolvers

ABSTRACT Design and measurement results of the signal converter with three-phase and quadrature outputs are presented in this paper. Input to the converter is a sinusoidal reference signal and the outputs are the quadrature and symmetrical three-phase sinusoidal signals of the same frequency as the reference. The output amplitudes are proportional to the reference amplitude. The quadrature output is generated in the novel phase-shift controlled all-pass filter, while the three-phase outputs are generated from the quadrature and reference signals in the electronic implementation of the Scott-T transformer. The converter is of all-analog design and is intended for driving receiver (Rx) type synchros and resolvers during testing and students hands-on laboratory experiments in the frequency range 50 Hz–5 kHz.

Wideband Dual Circularly Polarized Antenna for Intelligent Transport Systems

A wideband dual circularly polarized (DCP) antenna is presented for intelligent transport system (ITS) applications, which can be used to improve the receiver sensitivity and communication quality of ITS. The presented DCP antenna is composed of an orthogonal power divider (OPD) with two orthogonal input ports, four phase shifters for quadrature phase output, and four crossed dipoles for DCP radiation. Detailed equivalent circuit analysis shows that the OPD has two orthogonal inputs and four equal magnitude in-phase and out-of-phase outputs. To achieve two sets of orthogonal quadrature output signals for DCP radiation, the lumped element based differential right-hand transmission line unit cell and left-hand transmission line unit cell are elaborately introduced as the ±45° phase shifters, and incorporated into the OPD. Eventually, orthogonal quadrature signals are successfully obtained and fed to the crossed dipoles for DCP radiation. The proposed antenna was then designed, fabricated, and measured for ITS applications. The measured results show that the overlapped impedance bandwidth of both two input ports is 1.07–1.85 GHz (53.4%), and the isolation is higher than 15.2 dB. Moreover, low axial ratio (<1.7 dB) and symmetrical radiation patterns are achieved for unidirectional DCP radiation.

A 20–32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation

This article presents a broadband quadrature digital transmitter (TX) architecture for part of the fifth-generation new radio (5GNR) frequency range 2 (FR2) and backhaul communication. Synthesized impedance variation compensation (IVC) is introduced to improve the efficiency by manipulating the load impedance variation of sub-arrays in the power digital-to-analog converter (power-DAC) at mm-wave. The operation bandwidth is extended by 5 GHz with reconfigurable circuits of output matching in power-DAC, interstage matching, and quadrature signal generator. A mixed-signal sign map is adopted to provide LO gain as well as constellation quadrant selection. As a proof of concept, a 2×10 -bit 20-32-GHz quadrature digital TX is designed and fabricated in 28-nm CMOS technology. With a 1-V supply, the proposed quadrature digital TX achieves the peak output power of 19.02 dBm at 22.5 GHz, the peak drain efficiency of 34.4% at 22 GHz, and the peak system efficiency of 22.1% at 22 GHz. At 23/28 GHz, it demonstrates the EVM of -28.9/-28.4 dB, the average power of 9.96/9.17 dBm, and adjacent channel power ratio (ACPR) of -33.6/-33.3 dBc for 3-Gb/s 64-QAM modulation, respectively. It also supports 1-Gb/s 256-QAM modulation signal.

On the Enhancement of Generalized Integrator-Based Adaptive Filter Dynamic Tuning Range

Many phase-locked loop (PLL) or frequency-locked loop (FLL) use quadrature signals (directly or indirectly) as the input variables. Generalized integrator (GI) is a popular quadrature signal generator (QSG) available in the literature. GI is also widely used in various industrial applications. In addition to being a QSG, GI also works as a kind of bandpass filter. However, due to structural limitations, the dynamic tuning range is limited for the standard GI. The limitation arises from using only one gain in the direct-phase estimation dynamics, while quadrature phase estimation dynamics does not use direct feedback of the filter estimation error. Some attempts have already been made to overcome this limitation by adding direct feedback of the filter estimation error to quadrature-phase dynamics as well. However, we have demonstrated in this article that this kind of implementation has some frequency domain limitations. In this article, we propose a novel GI-type adaptive filter using coordinate transformation. The resulting structure maintains the same kind of filtering property of the standard GI at the transformed coordinates level while at the same time enhancing the dynamic tuning range of standard GI. Details of the proposed technique, stability analysis, and discussion on gain tuning are provided in this article. Finally, comparative experimental results are provided with respect to GI-FLL to show the dynamic performance improvement. Experimental results demonstrate the suitability of the proposed technique.

Semi-blind joint channel estimation and data detection on sphere manifold for MIMO with high-order QAM signaling

A low-complexity semi-blind scheme is proposed for joint channel estimation and data detection on sphere manifold for multiple-input multiple-output (MIMO) systems with high-order quadrature amplitude modulation signaling. Specifically, the optimal channel estimator is expressed in the least squares form in terms of the received signals and unknown transmitted data, and by splitting the channel and transmitted data into their real parts and imaginary parts, the data detection becomes a problem defined on a scaled sphere manifold in the real domain. Our semi-blind algorithm consists of three stages: (i) a few training symbols are employed to provide a rough initial MIMO channel estimate which in turn yields the initial zero-forcing (ZF) estimate of data samples; (ii) the Riemannian conjugate gradient algorithm is used to estimate the data samples in real domain, and the detected data samples are used to estimate the final MIMO channel matrix; and (iii) the final ZF data detection is carried out based on the final MIMO channel estimate. In particular, we present the first order Riemannian geometry of the sphere manifold which is utilized in the Riemannian conjugate gradient algorithm for solving (ii). Simulation results are employed to demonstrate the effectiveness of the proposed approach.

Four core properties of the human brain valuation system demonstrated in intracranial signals.

Estimating the value of alternative options is a key process in decision-making. Human functional magnetic resonance imaging and monkey electrophysiology studies have identified brain regions, such as the ventromedial prefrontal cortex (vmPFC) and lateral orbitofrontal cortex (lOFC), composing a value system. In the present study, in an effort to bridge across species and techniques, we investigated the neural representation of value ratings in 36 people with epilepsy, using intracranial electroencephalography. We found that subjective value was positively reflected in both vmPFC and lOFC high-frequency activity, plus several other brain regions, including the hippocampus. We then demonstrated that subjective value could be decoded (1) in pre-stimulus activity, (2) for various categories of items, (3) even during a distractive task and (4) as both linear and quadratic signals (encoding both value and confidence). Thus, our findings specify key functional properties of neural value signals (anticipation, generality, automaticity, quadraticity), which might provide insights into human irrational choice behaviors.

Phase Imbalance Optimization in Interference Linear Displacement Sensor with Surface Gratings.

In interferential linear displacement sensors, accurate information about the position of the reading head is calculated out of a pair of quadrature (sine and cosine) signals. In double grating interference schemes, diffraction gratings combine the function of beam splitters and phase retardation devices. Specifically, the reference diffraction grating is located in the reading head and regulates the phase shifts in diffraction orders. Measurement diffraction grating moves along with the object and provides correspondence to the displacement coordinate. To stabilize the phase imbalance in the output quadrature signals of the sensor, we propose to calculate and optimize the parameters of these gratings, based not only on the energetic analysis, but along with phase relationships in diffraction orders. The optimization method is based on rigorous coupled-wave analysis simulation of the phase shifts of light in diffraction orders in the optical system. The phase properties of the reference diffraction grating in the interferential sensor are studied. It is confirmed that the possibility of quadrature modulation depends on parameters of static reference scale. The implemented optimization criteria are formulated in accordance with the signal generation process in the optical branch. Phase imbalance and amplification coefficients are derived from Heydemann elliptic correction and expressed through the diffraction efficiencies and phase retardations of the reference scale. The phase imbalance of the obtained quadrature signals is estimated in ellipticity correction terms depending on the uncertainties of influencing parameters.

Ultra-wideband Quadrature LC-VCO using Capacitor-Bank and backgate topology with on-chip spirally stacked inductor in 0.13 ​μm RF-CMOS process covering S–C bands

Frequency tracking and synthesizer at the mm-wave range suffer an everlasting compromise between phase noise (PN) performance and frequency tuning range (FTR) irrespective of the topology adopted. This work proposes an Ultra-Wide Band, Quadrature Voltage Controlled Oscillator (QVCO) employing an on-chip inductor and 8-Bit Capacitor-Bank (Cap-Bank) in addition to the MOS-Varactors, to bring in the best compromise between above two said constraints. The additional efforts are kept generating Quadrature operation and keeping the power dissipation in an optimized range. It is shown that unlike conventional current reuse and wider MOS topology, the proposed Cap-Bank array with scaled transistor-based switches effectively widens the tuning operation with a remarkable FTR up to 85.7%, covering the most frequently used wireless standards IEEE-802.11 a/b/g of Bluetooth and Wi-Fi in S and C bands respectively. The design has been implemented with 0.13 ​μm RF-CMOS process in ADS (Keysight Technologies). The Back-Gate topology has been used with the cross-coupled differential structure which generates the quadrature phased signals well-shaped and with the least add on power dissipation. Use of a low-loss on-chip spirally stacked inductor, enhances the chip integrity, spectrum quality and improves Phase Noise performance, providing the best phase noise of −164 dBc/Hz at 1 ​MHz (near fmax) at a power dissipation of 12 ​mW from 1.2 ​V supply. The VCO gain achieved for the entire range of 2.4–6 ​GHz, varies largely from 1332 ​MHz/V (near fmax ​= ​6 ​GHz) to 42 ​MHz/V (near fmin ​= ​2.4 ​GHz) for the coarse tuning of Cap-Bank.

Deep Learning for RF Fingerprinting: A Massive Experimental Study

RF fingerprinting is a key security mechanism that allows device identification by learning unchanging, hardware-based characteristics of the transmitter. In this article, we demonstrate how machine learning techniques impact RF fingerprinting by analyzing a dataset of 400 GB of in-phase (I) and quadrature (Q) signal data transmitted by 10,000 radios. Our deep convolutional neural network architectures take raw and processed IQ samples as input to identify devices under a variety of practical conditions, including changing channels, noise levels, training data sizes, and computational overheads, among others. The contributions of the article are as follows: (i) This is the first work, to the best of our knowledge, reporting on RF fingerprinting and scalability issues on very large device populations, in the range of 50-10,000 devices. (ii) We investigate how to mitigate the effect of the wireless channel through a feature engineering step that we refer to as partial equalization. (iii) We provide a comprehensive performance evaluation of both a custom-designed and a modified ResNet architecture, with insights on which one may be preferred under specific environmental conditions.

A Compact I/Q Upconversion Chain for a 5G Wireless Transmitter in 65-nm CMOS Technology

A compact in-phase/quadrature (I/Q) upconversion chain with high linearity is presented for an integrated transceiver for 5G mobile communications. The upconverter includes 10–11.5-GHz upconversion chains, a quadrature signal generator (QSG) consisting of the two coupled current-mode logic latches, and inverting amplifiers to provide the rail-to-rail local oscillator (LO) swing with a 25% duty cycle for I/Q mixers which achieved 46.9 dB of image rejection ratio. A cross-coupled pair operating at weak inversion was used at the output of the upconverter and it improved the output of the third-order intercept point (OIP3) by 2.58 dB. The upconverter achieved a transmitter gain of 9.12 dB and an OIP3 of 14.45 dBm. The implemented I/Q upconverter with the QSG consumes 48.7 mW under a 1-V supply, and it occupies only 0.57 mm2 of chip area including pads.

A comparative study between Class-C and Class-B quadrature voltage-controlled power oscillator for multi-standard applications

In this paper a 0.35 ​mW Class-C/B series coupling quadrature voltage-controlled power oscillator (S-QVCO) based on the coupling between two identical LC VCOs is presented. The S-QVCO is designed using a 130 ​nm CMOS technology and it is suitable for multi-standard applications. High quality factor inductor is designed using the two top metal layers to enhance the phase noise performance of the VCO, also an improved switching varactor is used to achieve dual bands. The proposed QVCO achieves tuning range of 28.2% from 2.3 to 3.07 ​GHz, and low phase noise of −119.2 dBc at a 1-MHz offset frequency from 2.7 ​GHz carrier. By biasing the proposed QVCO in class-C, the DC current is reduced to 0.35 ​mA compared to 1.48 ​mA in class-B from 1 ​V supply voltage. The minimum achieved Figure-of-Merit (FOM) equals −192 dBc/Hz and the maximum given output power is 6.5 dBm. The phase error between quadrature output signals is maximum of 0.25° . The occupied area of the proposed QVCO equals0.34mm2, while the total chip area including RF pads is1mm2.