A 20–32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation

Abstract

This article presents a broadband quadrature digital transmitter (TX) architecture for part of the fifth-generation new radio (5GNR) frequency range 2 (FR2) and backhaul communication. Synthesized impedance variation compensation (IVC) is introduced to improve the efficiency by manipulating the load impedance variation of sub-arrays in the power digital-to-analog converter (power-DAC) at mm-wave. The operation bandwidth is extended by 5 GHz with reconfigurable circuits of output matching in power-DAC, interstage matching, and quadrature signal generator. A mixed-signal sign map is adopted to provide LO gain as well as constellation quadrant selection. As a proof of concept, a 2×10 -bit 20-32-GHz quadrature digital TX is designed and fabricated in 28-nm CMOS technology. With a 1-V supply, the proposed quadrature digital TX achieves the peak output power of 19.02 dBm at 22.5 GHz, the peak drain efficiency of 34.4% at 22 GHz, and the peak system efficiency of 22.1% at 22 GHz. At 23/28 GHz, it demonstrates the EVM of -28.9/-28.4 dB, the average power of 9.96/9.17 dBm, and adjacent channel power ratio (ACPR) of -33.6/-33.3 dBc for 3-Gb/s 64-QAM modulation, respectively. It also supports 1-Gb/s 256-QAM modulation signal.