Quad-level Cell Research Articles

Impact of Program-Erase Operation Intervals at Different Temperatures on 3D Charge-Trapping Triple-Level-Cell NAND Flash Memory Reliability.

Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost. The reliability property is becoming an important factor for NAND flash memory with multi-level-cell (MLC) modes like triple-level-cell (TLC) or quad-level-cell (QLC), which is seriously affected by the intervals between program (P) and erase (E) operations during P/E cycles. In this work, the impacts of the intervals between P&E cycling under different temperatures and P/E cycles were systematically characterized. The results are further analyzed in terms of program disturb (PD), read disturb (RD), and data retention (DR). It was found that fail bit counts (FBCs) during the high temperature (HT) PD process are much smaller than those of the room temperature (RT) PD process. Moreover, upshift error and downshift error dominate the HT PD and RT PD processes, respectively. To improve the memory reliability of 3D CT TLC NAND, different intervals between P&E operations should be adopted considering the operating temperatures. These results could provide potential insights to optimize the lifetime of NAND flash-based memory systems.

Data Placement Using a Classifier for SLC/QLC Hybrid SSDs

In hybrid SSDs (solid-state drives) consisting of SLC (single-level cell) and QLC (quad-level cell), efficiently using the limited SLC cache space is crucial. In this paper, we present a practical data placement scheme, which determines the placement location of incoming write requests using a lightweight machine-learning model. It leverages information about I/O workload characteristics and SSD status to identify cold data that does not need to be stored in the SLC cache with high accuracy. By strategically bypassing the SLC cache for cold data, our scheme significantly reduces unnecessary data movements between the SLC and QLC regions, improving the overall efficiency of the SSD. Through simulation-based studies using real-world workloads, we demonstrate that our scheme outperforms existing approaches by up to 44%.

Edge Word-Line Reliability Problem in 3-D NAND Flash Memory: Observations, Analysis, and Solutions

The 3-D flash memory is gradually becoming the mainstream nonvolatile storage medium due to its high capacity and high performance. However, interlayer interference during 3-D flash programming leads to significant differences in the error characteristics of edge and inner word lines; interlayer interference becomes more pronounced as the number of stacked layers increases, seriously affecting data storage reliability. In this study, many actual tests were conducted on triple-level cell (TLC) and quad-level cell (QLC) flash memory, which are the mainstream storage media in the current consumer market, to obtain the edge and inner word-line threshold voltage data under the interference of different factors, such as retention loss and read disturb; then, the threshold voltage difference between the edge and inner word lines under different conditions was quantitatively analyzed. An edge word-line reliability optimization strategy is proposed based on the read-reference voltage extra offset (RRVEO). Experimental results show that this strategy can reduce the edge word-line raw bit error rate (RBER) by more than 90% and eliminate the reliability difference between inner and edge word lines without significant overhead, thus significantly improving the data storage reliability of flash memory.

Performance and reliability optimization for high-density flash-based hybrid SSDs

Hybrid SSDs that integrate both large-capacity flash and high-performance flash have become the mainstream of the existing SSD architectures. Two or more flash modes have been supported to satisfy the complex and changeable application requirements, such as single-level-cell (SLC) mode and quad-level-cell (QLC) mode, which can be adaptively switched. However, our empirical studies show that the combination is not well-designed in existing hybrid architectures. We conduct experiments on different scenarios to study the performance and reliability of real hybrid SSDs. Three interesting findings about performance collapse, performance fluctuation, and read disturb of QLC region can be obtained. To solve these problems, this paper proposed HyFlex, including three novel schemes. First, a velocity-based I/O scheduling (VIS) scheme is a novel data placement scheme to avoid performance corrupt. Second, a garbage collection aware capacity tuning (GCT) scheme is a novel flash-mode management scheme to avoid burst performance degradation. Third, a read disturb-aware data migration (DAM) scheme is a novel data migration scheme to alleviate the read disturb of the QLC region. The experiments are conducted on an existing simulator with hybrid SSD extensions. Experimental results show that HyFlex achieves encouraging performance and reliability optimization.

고집적 낸드 플래시 SSD의 수명 및 쓰기 성능 향상을 위한 BER 기반 하이브리드 파티션 기법

낸드 플래시 기반 SSD (solid-state drive)는 제한된 P/E (program/erase) 사이클 횟수로 인한 내구성 문제로 TLC (triple-level cell)에서 QLC (quad-level cell)로 전환하는데 어려움이 있다. FTL (flash translation layer) 수준에서 내구성 문제를 해결하기 위해서는 블록의 수명을 예측하여 불량 블록 발생을 최소화하는 것이 중요하며, 이를 위해 비트 오류율 (bit error rate, BER)을 내구성 지표로 사용하여 수명을 균등하게 유지하는 방법이 사용되고 있다. 하지만 다중 레벨 셀 (MLC, TLC, QLC) 낸드 플래시의 일부를 SLC (single-level cell) 모드로 사용하는 하이브리드 SSD에서는 여전히 P/E 사이클을 기준으로 SLC 영역을 선정하고 있기 때문에 실제 SSD 수명과 불일치 가능성이 높아 효과적이지 않다. 본 논문에서는 하이브리드 SSD 파티션을 위해 내구성 지표로 BER을 사용하는 BDQS (BER Disparity based QLC to SLC mode programming) 기법을 제안한다. 동일한 수준의 BER을 가지는 QLC 블록들을 선별해 SLC 영역으로 전환하고 추가적으로 전환된 SLC 영역 블록의 BER을 보다 세분화해 콜드 (cold) 데이터 쓰기 버퍼, 핫 (hot) 데이터 저장 공간으로 활용함으로써 수명을 보다 개선시킬 수 있도록 한다. BDQS 기법은 쓰기 버퍼가 없는 기존 하이브리드 SSD 구조 대비 약 9.6%의 용량 감소가 발생하지만, SLC 저장 공간의 불량 블록 발생 시간이 최대 69.0%, 시스템 수명은 40.3% 연장되었고 그리고 baseline 대비 평균 쓰기 응답 시간도 22.0%까지 개선됨을 확인하였다.

Quad-Level Cell Switching with Excellent Reliability in TiN/AlOx:Ti/TaOx/TiN Memory Device.

TiN/AlOx:Ti/TaOx/TiN memory devices using bilayer resistive switching memory demonstrated excellent durability and capability of QLC (quad-level cell) memory devices. The best nonvolatile memory characteristics with the lowest operation current and optimized 4 bit/cell states were obtained using the Incremental Step Pulse Programming (ISPP) algorithm in array. As a result, a superior QLC reliability (cycle endurance > 1 k at each level of the QLC, data retention > 2 h at 125 °C) for all the 4 bits/cell operations was achieved in sub-μm scaled RRAM (resistive random access memory) devices.

Recent Progress on 3D NAND Flash Technologies

Since 3D NAND was introduced to the industry with 24 layers, the areal density has been successfully increased more than ten times, and has exceeded 10 Gb/mm2 with 176 layers. The physical scaling of XYZ dimensions including layer stacking and footprint scaling enabled the density scaling. Logical scaling has been successfully realized, too. TLC (triple-level cell, 3 bits per cell) is now the mainstream in 3D NAND, while QLC (quad-level cell, 4 bits per cell) is increasing the presence. Several attempts and partial demonstrations were made for PLC (penta-level cell, 5 bits per cell). CMOS under array (CuA) enabled the die size reduction and performance improvements. Program and erase schemes to address the technology challenges such as short-term data retention of the charge-trap cell and the large block size are being investigated.

Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell (MLC) RRAM operation without the need of any read verification. RRAM quad-level cell (QLC) capability with 4 bits/cell is demonstrated for the first time. QLC is implemented based on a strict control of the cell programming current of 1T-1R HfO2-based RRAM cells. From a design standpoint, a self-adaptive write termination circuit is proposed to control the RESET operation and provide an accurate tuning of the analog resistance value of each cell of a memory array. The different resistance levels are obtained by varying the compliance current in the RESET direction. Impact of variability on resistance margins is simulated and analyzed quantitatively at the circuit level to guarantee the robustness of the proposed MLC scheme. The minimal resistance margin reported between two consecutive states is 2.1 kΩ along with an average energy consumption and latency of 25 pJ/cell and 1.65 μs, respectively.

Investigation of Re-Program Scheme in Charge Trap-Based 3D NAND Flash Memory

Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND (Shibata et al. , 2007, Lee et al. , 2018, Shibata et al. , 2019, and Khakifirooz et al. , 2021), and the IVS improvement by re-program scheme was reported. In this work, it is found that re-program can suppress ~81% of IVS in 3D NAND, which is much more significant than that of 2D NAND ~50% (Chen et al. , 2010). The mechanisms of IVS improvement by re-program scheme in 3D NAND are investigated. Both vertical de-trapping in the BE-tunneling oxide and charge lateral migration (LM) in the charge-trap layer are suppressed in re-program. Re-program is effective in vertical de-trapping suppression both in checker-board pattern (C/P) and solid-board pattern (S/P) cases, and is effective in LM suppression only in C/P case. Furthermore, the LM improvement by re-program scheme is more pronounced with gate length (Lg) and inter-gate space (Ls) scaling down, showing potential in the reliability improvement of advanced 3D NAND technologies.

Building Reliable Massive Capacity SSDs through a Flash Aware RAID-Like Protection

The demand for mass storage devices has become an inevitable consequence of the explosive increase in data volume. The three-dimensional (3D) vertical NAND (V-NAND) and quad-level cell (QLC) technologies rapidly accelerate the capacity increase of flash memory based storage system, such as SSDs (Solid State Drives). Massive capacity SSDs adopt dozens or hundreds of flash memory chips in order to implement large capacity storage. However, employing such a large number of flash chips increases the error rate in SSDs. A RAID-like technique inside an SSD has been used in a variety of commercial products, along with various studies, in order to protect user data. With the advent of new types of massive storage devices, studies on the design of RAID-like protection techniques for such huge capacity SSDs are important and essential. In this paper, we propose a massive SSD-Aware Parity Logging (mSAPL) scheme that protects against n-failures at the same time in a stripe, where n is protection strength that is specified by the user. The proposed technique allows for us to choose the strength of protection for user data. We implemented mSAPL on a trace-based simulator and evaluated it with real-world I/O workload traces. In addition, we quantitatively analyze the error rates of a flash based SSD for different RAID-like configurations with analytic models. We show that mSAPL outperforms the state-of-the-art RAID-like technique in the performance and reliability.

Implementation of Data Search in Multi-Level NAND Flash Memory by Complementary Storage Scheme

We develop a novel scheme to realize data search in NAND flash memories, which is important for a wide variety of applications in data centers. In our design, the pair unit consists of double neighbor cells in the NAND string, one “data cell” and one “complementary cell”. The NAND string will be at the “Pass” state only when the searching data are completely matched with the stored data. Parameters that affect data search performance are analyzed systematically. Based on simulations in vertically stacked 3D NAND structures, it is shown that the bit-line current ratio of the fully matched case to the worst case of one mismatched data is more than ~104 in both MLC (multi-level cell) and TLC (triple-level cell) modes, and ~102 can still be obtained in QLC (quad-level cell) mode after read voltage optimizations. These results indicate that the proposed scheme is effective for data search in multi-level NAND flash memories and also friendly for peripheral circuits design.

HyFAT: Affordable Hybrid Fast Address Translating Device Driver for Multichannel-Based Flash Devices

Artificial intelligence (AI)-based consumer electronic (CE) devices generate massive amounts of accumulated hot data. Persisting this data into such devices’ storage media like the universal flash storage (USF) becomes an issue for flash storage system to manage hot data optimally. Consequently, efforts have been made to support many CE applications and achieve high performance and scalability storage in CE devices. However, it is challenging to find a compatible flash translation layer (FTL) for such flash devices, which can efficiently handle frequent updates imposed by the incoming hot data. Moreover, FTL should be able to handle the hot multimedia data that induces cache-miss penalties which in-turn degrades our flash storage performance. This paper proposes a hybrid flash device for fast address translations called HyFAT which is workload-compatible. HyFAT improves device performance and efficiently manages the combined QuadLevel cell (QLC) for data storage and scalability with SingleLevel cell (SLC) for fast mapping entry storage. The experimental results with realistic workloads show that our approach can improve device performance throughput by 18% on average, compared to traditional DFTL and RFTL.

Compound Mapping and Filter Algorithm for Hybrid SSD Structure

With the recent development of byte-unit non-volatile random access memory (RAM), various methods utilizing quad level cell (QLC) not-AND (NAND) flash memory with non-volatile RAM have been proposed. However, tests have shown that these hybrid structures lead to a reduction in the performance of a hybrid solid state disk (SSD) owing to issues regarding space efficiency. This study proposes a compound address method and filter algorithm suitable for the next generation of NAND flash, called hybrid storage media, where QLCs and phase-change memory (PCM) are used together. The filter-mapping algorithm includes a management method that stores data in phase-change memory or flash memory according to the next command, which is accessed when a write command that is half or less than half a page in length is received from the file system. Tests have shown that the compound mapping and filter algorithm reduces the wasted pages by more than half and the number of merge operations is also significantly decreased. This leads to a decrease in the number of delete operations and improves the overall processing speed of the hardware.

Quad-level cell NAND design and soft-bit generation for low-density parity-check decoding in system-level application

QLC (Quad-Level Cell) NAND flash will be one of the future technologies for next generation memory chip after three-dimensional (3D) TLC (Triple-Level Cell) stacked NAND flash. In QLC device, data errors will easily occur because of 24 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on “half-change” Gray coding are researched. Because of the probable error impact of QLC NAND cell’s voltage change, the solution of generating the soft information after XOR (exclusive OR) the soft bits by internal read mechanism is presented for Low-Density Parity-Check (LDPC) Belief Propagation (BP) decoding in QLC design for its system level application.

Efficient Page Collection Scheme for QLC NAND Flash Memory using Cache

Recently, semiconductor companies such as Samsung, Hynix, and Micron, have focused on quad-level cell (QLC) NAND flash memory chips, because of the increase in the capacity of storage systems. The QLC NAND flash memory chip stores 4 bits per cell. A page in the QLC NAND flash memory consists of 16 sectors, which is two to four times larger than that of conventional triple-level cell flash NAND flash memory. Because of its large page size, when the QLC NAND flash memory is applied to the current storage system directly, each page space is not efficiently used, resulting in low space utilization in overall storage systems. To solve this problem, an efficient page collection scheme using cache for QLC NAND flash memory (PCS) is proposed. The main role of PCS is managing the data transmitted from the file system efficiently (according to the data pattern and size), and reducing the number of unnecessary write operations. The efficiency of PCS was evaluated using SNIA IOTTA NEXUS5 trace-driven simulation on QLC NAND flash memory. According to close observation, PCS significantly reduces 50% of write operations compared with previous page collection algorithms, by efficiently collecting the small data into a page. Furthermore, a cache idle-time determination algorithm is proposed to further increase the space utilization of each page, thereby reducing the overall number of write operations on the QLC flash memory.

FTL Algorithm using Warm Block Technique for QLC+SLC Hybrid NAND Flash Memory

When applying the existing flash translation layer technique to a mixed NAND flash storage device composed of Quad Level Cell and Single Level Cell, because the characteristics of a semiconductor chip are not taken into consideration, the data are stored indiscriminately, and thus the performance and stability are not guaranteed. Therefore, this study proposes a flash translation layer algorithm using the warm block technique in a NAND flash storage device that combines a large capacity Quad Level Cell and a high performance Single Level Cell. The warm block technique avoids overloading of the read/write/erase operations in the Quad Level Cell flash memory by efficiently placing hot data that are frequently updated on a long-living Single Level Cell. It was confirmed experimentally that the lifetime extension and performance of hybrid NAND flash memory are improved using the warm block technique.

QLC NAND study and enhanced Gray coding methods for sixteen-level-based program algorithms

After the development of TLC (Triple level cell) NAND, QLC (Quad level cell) technology will be one of the solutions for next generation NAND flash product. QLC (4 bits/cell) NAND's data levels are up to 16 levels which bring the narrower and tighter voltage ranges and worse performance. This paper studies QLC program and read mechanisms, and presents five types of program algorithms for writing data in QLC cells. Correspondingly, the enhanced Gray coding methods for data mapping based on these different program algorithms are researched. They will be beneficial to data reading. After simulating with changing cell voltages to generate the data errors in the QLC model, the paper presents four enhanced Gray codings to match 16 voltage levels for different program algorithms and read operations. This study will improve the efficiency and keep balance in system-level application for the data error correction of QLC 4 pages which are mapped in the same wordline (WL).