Abstract
Recently, semiconductor companies such as Samsung, Hynix, and Micron, have focused on quad-level cell (QLC) NAND flash memory chips, because of the increase in the capacity of storage systems. The QLC NAND flash memory chip stores 4 bits per cell. A page in the QLC NAND flash memory consists of 16 sectors, which is two to four times larger than that of conventional triple-level cell flash NAND flash memory. Because of its large page size, when the QLC NAND flash memory is applied to the current storage system directly, each page space is not efficiently used, resulting in low space utilization in overall storage systems. To solve this problem, an efficient page collection scheme using cache for QLC NAND flash memory (PCS) is proposed. The main role of PCS is managing the data transmitted from the file system efficiently (according to the data pattern and size), and reducing the number of unnecessary write operations. The efficiency of PCS was evaluated using SNIA IOTTA NEXUS5 trace-driven simulation on QLC NAND flash memory. According to close observation, PCS significantly reduces 50% of write operations compared with previous page collection algorithms, by efficiently collecting the small data into a page. Furthermore, a cache idle-time determination algorithm is proposed to further increase the space utilization of each page, thereby reducing the overall number of write operations on the QLC flash memory.
Highlights
In recent years, the solid-state drive (SSD) market has grown rapidly owing to the capacity increase of storage systems
quad-level cell (QLC) NAND flash memory stores four bits in a single cell; the capacity can be increased more compared with Single-level cell (SLC)/multilevel cell (MLC)/tri-level cell (TLC) NAND flash memories NAND flash memories commonly consist of a “page” in read/write operation units, and several pages are gathered and compose a “block,” which is a unit of erase operation
A page collection method that uses cache was investigated for QLC NAND flash memory
Summary
The solid-state drive (SSD) market has grown rapidly owing to the capacity increase of storage systems. QLC NAND flash memory stores four bits in a single cell; the capacity can be increased more compared with SLC/MLC/tri-level cell (TLC) NAND flash memories NAND flash memories commonly consist of a “page” (a set of sectors) in read/write operation units, and several pages are gathered and compose a “block,” which is a unit of erase operation. The proposed Page Collection Scheme was tested through SNIA IOTTA‟s Nexus 5 Smartphone Traces-based simulation, and the results showed a large increase in the number of pages that had good space utilization and a decrease in the number of write operations, as discussed in Section 3.The rest of this work is structured as follows. To increase the low space utilization of these pages that are operated inefficiently, a page collection method using a cache is proposed
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