Abstract
Since 3D NAND was introduced to the industry with 24 layers, the areal density has been successfully increased more than ten times, and has exceeded 10 Gb/mm2 with 176 layers. The physical scaling of XYZ dimensions including layer stacking and footprint scaling enabled the density scaling. Logical scaling has been successfully realized, too. TLC (triple-level cell, 3 bits per cell) is now the mainstream in 3D NAND, while QLC (quad-level cell, 4 bits per cell) is increasing the presence. Several attempts and partial demonstrations were made for PLC (penta-level cell, 5 bits per cell). CMOS under array (CuA) enabled the die size reduction and performance improvements. Program and erase schemes to address the technology challenges such as short-term data retention of the charge-trap cell and the large block size are being investigated.
Highlights
After 2D NAND reached the scaling limit around 15 nm in process node, 3D NAND was proposed as a solution for the continuous NAND scaling [1]
The scaling trend of the areal density of 2D NAND and 3D NAND is summarized based on the NAND publications in IEEE ISSCC conferences, (Figure 1)
In the charge-trap cells, the programming is similar to floating gate (FG) cells, where the electrons are injected to the SiN storage by modified FN tunneling
Summary
After 2D NAND reached the scaling limit around 15 nm in process node, 3D NAND was proposed as a solution for the continuous NAND scaling [1]. NAND strings are connected to the Si-substrate, and holes are string from the. Supplied to the NAND string from the Si-substrate, enabling the positive body potential. In the GIDL erase, the NAND strings are de-decoupled from the Si-substrate and formed on required for erase. In the GIDL erase, the NAND strings are de-decoupled from the Sithe N+ source layer instead. The electron-hole pairs are generated at source and substrate andstrings. During erase,Array the electron-hole pairs the NAND is used the CMOS under (CuA) technology, drain N+ junctions by GIDL mechanism to supply holes to the NAND strings. (b) GIDL erase scheme generates electron-hole pairs at the source and drain junctions.
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