Quad Flat Non-lead Research Articles

Analysis and Design of Current Mode Class-D Power Amplifiers With Finite Feeding Inductors

Current-mode class-D (CMCD) power amplifiers (PAs) may not achieve a switching efficiency as good as class-E PAs, but they require fewer inductances and deliver almost five times more power for the same load and supply voltage when compared with the ideal push–pull class-E PA. Furthermore, CMCD PAs can easily use bondwires as the only circuit inductors, a precious feature that Internet-of-Things (IoT) wireless interfaces can exploit. For this reason, we analyze the voltage and current waveforms in CMCD PAs without assuming infinite value feeding inductors (i.e., without choke inductors). It is shown that the current stress on the switching device is significantly higher than in the conventional topology, especially in bondwire-based designs where relatively small feeding inductances are presented. Finally, we propose a design procedure for a given feeding inductance that maximizes energy efficiency while delivering a compact-size solution. A 2.4-GHz PA capable of delivering 19.8 dBm to a 100- $\Omega $ differential load with a power-added-efficiency (PAE) of 58% is presented. Three-dimensional electromagnetic (3-D EM) simulations combined with postlayout simulations were used to evaluate the PA performance in a quad-flat nonlead (QFN)-type package. The circuit is designed in a 0.13- $\mu \text {m}$ process and only occupies a silicon area of 0.025 mm2.

Investigation of natural convection heat transfer performance of the QFN-PCB electronic module by using nanofluid for power electronics cooling applications

Natural convection heat transfer of Cu-water nanofluid in a 3 × 3 array of a typical isothermal quad flat non-lead (QFN) embedded printed circuit board (PCB) module which can be bounded with respect to the sealed non-Darcy porous enclosure is numerically investigated. The Darcy-Brinkman-Forchheimer model is adopted to model the fluid flow in the porous medium under the presence of an external magnetic field. The transport governing equations are solved by the finite volume method based on the SIMPLE algorithm and the power law scheme. Main efforts focus on the effects of the parameters such as a nanoparticle volume fraction, Hartmann number, Darcy number and the enclosure side aspect ratio on the fluid flow and heat transfer characteristics inside the enclosure. The obtained results indicate that the influence of nanofluid of the overall Nusselt number increases with increasing the Darcy number, but decreases with increasing the Hartmann number. The overall Nusselt number attains its maximum value in the range of enclosure side aspect ratio from 1.5 to 3 with respect to the Darcy number. Moreover, the proposed correlations improve the efficiency, reliability and stability of the electronic device encountered in various applications in electronic industries.

Embarked Quad Flat Nonlead 16, 32, and 64 Electronic Devices Subjected to Free Convection: Influence of the Adhesive Paste on the Junction Temperature

The junction temperature of the quad flat nonlead (QFN) electronic devices equipping embarked assemblies may be controlled so that it does not exceed the maximum value recommended by the manufacturer. The packaging design is then important to ensure correct operation and high reliability, given the significant power generated during operation and the inclination angle of the packages during the flight. It is particularly important when thermoregulation is achieved by means of natural convection. The objective of this study is to examine the influence of the adhesive paste used to connect the Die of the QFN with its base. The study deals with three devices among the most used in the conventional arrangements: the QFN16, 32, and 64. A three-dimensional (3D) numerical solution based on the control volume formulation allows to determine their thermal behavior for generated power ranging from 0.1 to 1.0 W by steps of 0.1 W and inclination angle varying between 0 deg (horizontal position) and 90 deg (vertical position) by steps of 15 deg. A wide range of the paste’s thermal conductivity has been considered, varying between −80% and +100% of its average value, measured by means of the transient plane source (TPS) method. The numerical results confirmed by measurements show that the junction temperature strongly increases when the conductivity of the paste decreases. The temperature is moderately reduced when the paste is thermally more conductive. Relationships are proposed to calculate the junction temperature for the three considered devices, according to the generated power, the inclination angle, and the relative paste’s thermal conductivity.

Quantification of free convection for embarked QFN64 electronic package: An experimental and numerical survey

Embarked Quad Flat Non-lead (QFN) electronic devices are equipped with a significant number of sensors used for flight parameters measurement purposes. Their accuracy directly depends on the package thermal state. Flight safety therefore depends on the reliability of these QFNs, whose junction temperature must remain as low as possible while operating. The QFN64 is favored for these applications. In the operating power range considered here (0.01-0.1W), the study shows that radiative heat transfer is negligible with respect to natural convective exchanges. It is then essential to quantify the convective heat transfer coefficient on its different areas so that the arrangement is properly dimensioned. This is the objective of this work. The device is welded on a PCB which may be inclined with respect to the horizontal plane by an angle ranging from $0^{\circ}$ to $90^{\circ}$ . Numerical approach results are confirmed by thermal and electrical measurements carried out on prototypes for all power-inclination angle combinations. The correlations here proposed help determine the natural convective heat transfer coefficient in any area of the assembly. This work allowed to thermally characterize and certify a new QFN64 package equipped with sensors designed for aeronautics, currently under industrialization process.

Junction temperature of QFN32 and 64 electronic devices subjected to free convection. Effects of the resin's thermal conductivity

The thermal state of the electronic devices used in many engineering fields must be controlled. The maximum temperature does not exceed the value recommended by the manufacturer to prevent a decrease of their reliability, malfunction or decommissioning. The junction temperature of the Quad Flat Non-Lead (QFN) device which often equips the electronic assemblies is affected by the thermal characteristics of its components, in particular the thermal conductivity of the molding compound (resin) used for the package encapsulation. This work deals with the QFN32 and QFN64 models widely used in the field of smart building. These devices may be tilted of any angle from the horizontal and vertical positions, depending on where they are located in the considered building. The packages located in small boxes are subjected to air natural convection. The 3D numerical approach based on the volume control method considers several configurations obtained by varying the generated power between 0.01 and 0.1W by steps of 0.01W, corresponding to the partial operation. The junction thermal state is determined for many values of the resin's thermal conductivity ranging between −80% and +100% of its average value and inclination of the devices varying between 0 and 90° (horizontal and vertical positions respectively) by steps of 15°. The results of the numerical solution are confirmed by thermal and electrical measurements carried out in situ on various prototypes. The deviation between measurements and calculations is low, ranging between −3 and +7%. New and accurate relationships are proposed, allowing to improve the thermal design of the QFN32 and QFN64 packages by determining their junction temperature for any combination of the considered generated power, tilt angle and thermal conductivity of the encapsulating resin. The control of the thermal aspect allows to enhance substantially the reliability of these widely used electronic devices.

Thermal design of a sensor for building control equipped with QFN electronic devices subjected to free convection. Effects of the encapsulating resin

This work deals with thermal design of a sensor used in modern building for equipment control, equipped with Quad Flat Non-Lead (QFN) electronic device. The junction temperature of this package is affected by the thermal characteristics of its components, especially the thermal conductivity of the resin used for its encapsulation. To ensure its reliability during operation, the junction temperature must be controlled so that the maximum value recommended by the manufacturer isn’t exceeded. This aspect is examined in this work for 3 common devices, the QFN16b, 32b and 64b, which differ from their basic versions QFN16, 32 and 64 by the existence of a high conductive wires network connecting the active source to the leads. Several configurations are discussed in this work. The power generated during operation varies between 0.1 and 1.0W by steps of 0.1W and the resin’s thermal conductivity between −80% and +100% of its average value measured by means of the Transient Plane Source method. The inclination angle also plays an important role in the thermal state of these devices. It varies between 0 and 90° (horizontal and vertical positions respectively) by steps of 15°. The results obtained by means of a 3D numerical approach based on the volume control method are confirmed by thermal and electrical measurements. The junction temperature of the three examined devices can be calculated with relationships proposed in this survey for all the considered geometric and thermal configurations. These tools optimize the thermal design of these packages widely used in building field, improve their performance and ensure a high reliability.

Free convective heat transfer coefficient for high powered and tilted QFN64 electronic device

Heat exchanges occurring between the electronic assemblies and their environment are an essential data in order to control their temperature, enhance their performance and improve their reliability. In this survey, the average natural convective heat transfer coefficient is determined for an assembly constituted by a Quad Flat Non-lead QFN64 generating a high power ranging from 0.1 to 1.0W during operation. It is welded on a PCB which may be inclined with respect to the horizontal plane by an angle varying between 0° and 90°. The calculations done by means of the finite volume method show how the free convective heat transfer on every part of this electronic assembly is influenced by these physical parameters. The correlations proposed in this work allow calculating the convective heat transfer coefficient in any area of the considered assembly according to the generated power and the tilt inclination. These original and unpublished tools allow increasing reliability and better thermal control of this conventional device widely used in electronics for many engineering applications.

Free convective overall heat transfer coefficient on inclined electronic assembly with active QFN16 package

Purpose – The purpose of this paper is to determine the overall free convective heat transfer coefficient for an assembly constituted by a Quad Flat Non-lead QFN16 welded on a Printed Circuit Board (PCB) which may be inclined with respect to the horizontal plane by an angle varying between 0° and 90° corresponding to the horizontal and vertical position, respectively. This electronic device widely used in electronics generates during its effective operation a power ranging from 0.1 to 0.8 W. The assembly is installed in an air-filled cavity. Design/methodology/approach – Calculations are done by means of the finite volume method for many configurations obtained by varying the generated power, the inclination angle and the position of the QFN16 on the PCB. The dynamic and thermal aspects are presented and commented. Findings – The study shows that the thermal state of the electronic device is influenced by the previous three physical parameters. A correlation between the global convective exchange coefficient, the generated power and the PCB inclination angle is proposed in this survey. Practical implications – The results of this survey allow a better thermal control of this conventional arrangement widely used in electronic applications. Originality/value – The correlations proposed in this work are original and unpublished. The considered power varies between 0.1 and 0.8W corresponding to the effective operation of the device, associated to a PCB inclination angle ranging between 0° and 90°.

A novel gravitational search algorithm for multilevel image segmentation and its application on semiconductor packages vision inspection

Multilevel image segmentation is an important technique and indispensable process in vision inspection on semiconductor packages to sort out defective products from the qualified ones, classify and identify the defect types. Conventional multilevel image segmentation methods are computationally expensive, and lack accuracy and stability. To address this issue, this paper proposes a novel gravitational search algorithm (NGSA) for multilevel image segmentation. Two major improvements to the update mechanism (UM) have been made in NGSA, i.e., adaptive gravitational constant and normal mutation of global best agent, to help agents jump out of local optima and improve the calculation accuracy. The experimental results based on multilevel Otsu criterion demonstrate that the proposed NGSA can obtain optimal multilevel thresholds for the quad flat non-lead (QFN) defect images and the segmentation results are promising. Three different methods, firefly algorithm (FA), cuckoo search (CS) and gravitational search algorithm (GSA), are compared with the proposed method. Numerical illustrations show that the proposed NGSA outperforms FA and GSA, and performs as well as, or is better than CS in solution quality, computational efficiency, and operation stability. Hence, NGSA in combination with multilevel Otsu criterion can be accurately and efficiently used in multilevel image segmentation of vision inspection on semiconductor packages.

Effects of the wire-bonding technique on the QFN16b's thermal performance. New correlations for the free convective heat transfer coefficient

The technique of wire-bonding used in electronics is interesting for thermoregulation of the quad flat non-lead (QFN) packages during operation. To properly size these devices in the assemblies, it is necessary to know the surfacic thermal phenomena represented by the convective heat transfer coefficient. This is the objective of this work examining the thermal effects due to installation of wire-bonding on a QFN16. This particular device is named here QFN16b to differentiate it from the basic model without wire-bondings addressed in a previous study. During its actual operation, it generates a power ranging from 0.1W to 1.0W and it is welded on a printed circuit board (PCB) which could be inclined at different angles varying between the horizontal and vertical positions, according to the intended application. Calculations corresponding to 6 different areas of the considered assembly have been done by combining 20 powers generated by the QFN and 7 inclination angles. The distribution of the surface temperature and that of the source itself, as well as the free convective power exchanged by every area, are determined. Natural convective heat transfer is quantified by means of correlations which allow calculation of the average convective heat transfer coefficient in each area of the assembly and for all the treated configurations. They improve design, reliability, durability and performance of these conventional assemblies widely used in electronics in many engineering sectors.

Chip Last Fan Out as an Alternative to Chip First

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, and they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), and system in package (SIP) being widely used in these smart phones & mobile devices.. Fan out WLCSP (FOWLP) has great potential to be the next new package for the smart phone mobility application. Two factors have driven fan out WLCSP (FOWLP) package technology in the last few years. The first is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solder ball interconnects. The second and potentially more important factor relates to the demand of the market for more functions. Not all silicon functionality benefits from these advanced nodes, and merely adds to the cost of the die. This has driven the designers to partitioning of desired functionality into multiple die, which in turn requires effective interconnection of these separate die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). Up to date FOWLP used chip first processing, in which the bare die was molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a new alternative to chip first FOWLP, an alternative which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package has been in production in ASE for over a year, and uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented. We have designated this package structure “Fan Out Chip Last Package (FOCLP)” For higher end applications we will show the ability to use a high density substrate process for use in more demanding chip last fan out packages

Natural convection on inclined QFN32 electronic package generating constant volumetric heat flux

Qualification and quantification of the natural convective phenomena are examined in the case of a Quad Flat Non-lead (QFN32). This active electronic package is inclined with respect to the horizontal plane by an angle varying between 0° and 90° corresponding to the horizontal and vertical position respectively. It generates during its operation a constant volumetric heat flux leading to Rayleigh numbers varying in the range 1.31x107‐1.01x108. The walls of the large air-filled cubic cavity containing this device are maintained isothermal. The temperature and velocity fields are presented for different combinations of the Rayleigh number and inclination angle. The convective heat transfer concerning the whole component exchange surface is determined for all the treated configurations. Correlations of Nusselt–Rayleigh type are proposed. They allow optimizing the thermal design of electronic assemblies used in various engineering domains.

Low Cost Chip Last Fanout Package using Coreless Substrate

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, but at the same time they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), fan out WLCSP (FOWLP) and system in package (SIP) being widely used in these smart phones & mobile devices. Two factors have driven a new package technology within the last 10 years. One is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solderball interconnects. The second factor also relates to the advancing technology nodes. Not all silicon functionality benefits from there advanced nodes, and merely adds to the cost of the die. This has driven the partitioning of device functionality into multiple die, which in turn requires effective interconnection of these partitioned die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). The typical FOWLP uses chip first processing, in which the bare die is molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a relatively low cost alternative to FOWLP, which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. All previous FOWLP designs at ASE were able to be routed in a single layer using this new packaging technology . Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented.

Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modelling (XRD/3DSM) for non-destructive analysis of manufacturing process-induced stress/warpage inside completely encapsulated packaged chips. The technique is demonstrated at room temperature and at elevated temperatures up to 115°C by in situ XRD annealing experiments. The feasibility of this technique is confirmed through the characterisation of die stress inside encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing process.

Reliability Design of Multirow Quad Flat Nonlead Packages Based on Numerical Design of Experiment Method

A design of experiment (DOE) methodology based on numerical simulation is presented to improve thermal fatigue reliability of multirow quad flat nonlead (QFN) packages. In this method, the influences of material properties, structural geometries, and temperature cycling profiles on thermal fatigue reliability are evaluated, a L27(38) orthogonal array is built based on Taguchi method to figure out optimized factor combination design for promoting thermal fatigue reliability. Analysis of variance (ANOVA) is carried out to examine the influence of factors on the thermal fatigue reliability and to find the significant factors. Anand constitutive model is adopted to describe the viscoplastic behavior of lead-free solder Sn3.0Ag0.5Cu. The stress and strain in solder joints under temperature cycling are studied by 3D finite element (FE) model. The modified Coffin–Manson model is employed to predict the fatigue life of solder joints. Results indicate that the coefficients of thermal expansion (CTE) of printed circuit board (PCB), the height of solder joint, and CTE of epoxy molding compound (EMC) have critical influence on thermal fatigue life of solder joints. The fatigue life of multirow QFN package with original design is 767 cycles, which can be substantially improved by 5.43 times to 4165 cycles after the optimized factor combination design based on the presented method.

Applying CHAID algorithm to investigate critical attributes of void formation in QFN assembly

Purpose – The purpose of this paper is to employ data mining as a new diagnosing scheme for investigating void formation to the thermal pad in quad flat non‐lead (QFN) assembly. Occurrences of voiding in various scenarios of component design, materials selection and manufacturing process are analyzed.Design/methodology/approach – This research investigates the process yield of a PCB assembly for a handheld device in the electronics manufacturing industry using the chi‐square automatic interaction detection (CHAID) algorithm and chi‐square test. Practical data generated by an X‐ray apparatus from the shop floor are collected. The critical attributes to the void formation (in the solder joint) of the QFN component are identified.Findings – Stocking the PCB material beyond ten days may increase the level of voiding by 1%. Using PCB provided by vendor U helps decrease the level of voiding by 1.6%. Stocking the component material above 43 days may increase the level of voiding by 1.9%. In addition, reflow sold...

Power and signal integrity co-design for quad flat non-lead package

The co-design of power and signal integrity issues on a quad flat non-lead (QFN) package is described. A novel decoupling capacitor is achieved by separating the die pad and footprint, coating a solder mask on the footprint and connecting the footprint to the printed circuit board power plane through a via. Large capacitance between power (footprint) and ground (die pad) resulted from the thin mask and large die pad lowering the input impedance of the power delivery network without parasitic effects at low frequency. A power bridge and a ground bridge are introduced to substitute the wire bond to decrease the inductance and hence the impedance magnitude up to 30%, thus enhancing the power integrity at high frequency. A modified design called hybrid power/ground exhibits great signal integrity by providing good reference for signals. The thermal dissipation is also better than the first design through direct contact of the die pad and the footprint ground regions. The overall design demonstrates excellent broadband performance for signal and power integrity.

Reliability Evaluation of QFN Devices Soldered Joints with Creep Model

The solder joint reliability of quad flat non-lead (QFN) package,which has become very popular over the past few years,has received intense interest.The finite element method (FEM) is essential to evaluate the reliability of QFN device.In this paper,Garofalo-Arrheninus model was implemented to simulate the deformation of QFN soldered joints.Equivalent creep strain of the soldered joints was calculated by means of finite element analyses,and was used to evaluate the reliability of QFN packages.It is found that the critical soldered joint of QFN is located the package corner while the maximum creep strain is obtained at the top interface of peripheral soldered joint.The creep strain is provided with periodicity and additivity as the thermal cycling.Nonlinear analysis of QFN package with different lead counts was presented as well,in which the phenomenon that the value of induced creep strain arise as the package size decreasing is noted.Moreover,SnPb and two lead-free solders,namely,Sn3.5Ag/Sn3.8Ag0.7Cu,were both taken into consideration.Simulated results indicate that the creep strain value of lead-free soldered joints is lower than that of SnPb soldered joints,which can be attributed to the difference of stiffness and coefficient of thermal expansion among three solders.Garofalo-Arrheninus model is used to calculate the creep strain of the QFN device for the first time in this study.The results provide an important basis for evaluating the reliability of QFN package.

The use of grey relational analysis to determine laser cutting parameters for QFN packages with multiple performance characteristics

This paper reports an application of the grey relational analysis (GRA) to directly optimize laser cutting of a quad flat non-lead (QFN) strip using six performance characteristics. The most important performance characteristics include the cutting depth, the width of heat affected zone (HAZ), and the width of cutting line for both epoxy and Cu+epoxy materials along the cutting path. During the GRA, higher grades are obtained from any of the deeper (more complete) cutting depth, reduced widths of the HAZ and reduced widths of the cutting line. From nine experiments based on the orthogonal array of L9(3 4), a current of 29 A, a frequency of 2 kHz, and a cutting speed of 2 mm/s were found to be the best parameters for laser cutting of a QFN strip with a thickness of 0.9 mm. Moreover, the analysis of variance (ANOVA) is also employed to determine the contribution of each control parameter on the cutting quality characteristics. The three largest measured contributions on the cutting quality in decreasing order are the frequency, the current, and the cutting speed. Compared with the Taguchi optimization method, the GRA approach is significantly simpler because it directly assigns appropriate weighting factors to the required qualities. Finally, confirmation experiments are performed to ensure the robustness of the GRA predicted optimal configuration for laser cutting a QFN strip.

Optimal laser-cutting parameters for QFN packages by utilizing artificial neural networks and genetic algorithm

In this paper, a multiple regression analysis (MRA) and an artificial neural network (ANN) were employed to build a predicting model for cutting Quad Flat Non-lead (QFN) packages by using a Diode Pumped Solid State Laser (DPSSL) System. The predicting model includes three input variables of the current, the frequency and the cutting speed, and six cutting qualities of depths of the cutting line, widths of heat affected zone (HAZ) and cutting line for epoxy and for copper-compounded epoxy. After the training process from 27 sets of training data including input data and its output qualities, the average training error is 0.822% by using a back-propagation (BP) neural network with Levenberg–Marquardt (LM) algorithm, which leads to the best results. The testing accuracy is then verified with extra 14 sets of experimental data and the average predicting error is 1.512%. The results show that the ANN model has the predicting ability to estimate the laser-cutting qualities of QFN packages. Finally, a genetic algorithm (GA) is applied to find the optimal cutting parameters that lead to least HAZ width and fast cutting speed with complete cutting. The optimal combination found is the current of 29 A, the frequency of 2.7 kHz and the cutting speed of 3.49 mm/s. The GA is helpful to determine the ideal laser-cutting parameters in order to meet the desired cutting qualities and to avoid unnecessary adjustments in the subsequent cutting process.