Low Cost Chip Last Fanout Package using Coreless Substrate

Abstract

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, but at the same time they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), fan out WLCSP (FOWLP) and system in package (SIP) being widely used in these smart phones & mobile devices. Two factors have driven a new package technology within the last 10 years. One is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solderball interconnects. The second factor also relates to the advancing technology nodes. Not all silicon functionality benefits from there advanced nodes, and merely adds to the cost of the die. This has driven the partitioning of device functionality into multiple die, which in turn requires effective interconnection of these partitioned die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). The typical FOWLP uses chip first processing, in which the bare die is molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a relatively low cost alternative to FOWLP, which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. All previous FOWLP designs at ASE were able to be routed in a single layer using this new packaging technology . Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented.