Quasi-cyclic Low-density Parity-check Research Articles

High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

Lifting method for quasi-cyclic low-density parity-check codes based on approximated cycle extrinsic message degree in optical communication systems

Quasi-cyclic low-density parity-check (QC-LDPC) codes with low-complexity hardware implementation and excellent performance have become a hot research topic in many optical communication systems. To meet the different requirements of code lengths in optical communication systems, lifting methods which remove all the short cycles equally are usually used to construct long QC-LDPC codes of larger lengths by lifting short QC-LDPC codes. A lifting method is proposed, which considers both length and connectivity of short cycles. The proposed lifting method reduces the complexity of calculating the approximated cycle extrinsic message degree -related metrics and improves connectivity of the Tanner graph. The numerical results prove that, by employing our proposed lifting method, the lifted long QC-LDPC codes have better bit error rate performance compared with the lifted codes employing the traditional lifting method.

Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

Quasi-Cyclic LDPC Codes With Parity-Check Matrices of Column Weight Two or More for Correcting Phased Bursts of Erasures

In his pioneering work on LDPC codes, Gallager dismissed codes with parity-check matrices of weight two after proving that their minimum Hamming distances grow at most logarithmically with their code lengths. In spite of their poor minimum Hamming distances, it is shown that quasi-cyclic LDPC codes with parity-check matrices of column weight two have good capability to correct phased bursts of erasures which may not be surpassed by using quasi-cyclic LDPC codes with parity-check matrices of column weight three or more. By modifying the parity-check matrices of column weight two and globally coupling them, the erasure correcting capability can be further enhanced. Quasi-cyclic LDPC codes with parity-check matrices of column weight three or more that can correct phased bursts of erasures and perform well over the AWGN channel are also considered. Examples of such codes based on Reed-Solomon and Gabidulin codes are presented.

A Miniaturized LDPC Encoder: Two-Layer Architecture for CCSDS Near-Earth Standard

Quasi-cyclic low-density parity-check (QC-LDPC) codes, which have been adopted by the Consultative Committee for Space Data Systems (CCSDS), are widely used in Deep-Space (AR4JA) and Near-Earth (C2) communications. A large number of encoder architectures with CCSDS recommended standard have been proposed. But the existing architectures are not efficient enough in high-throughput implementations, many architectures have a lot of logical resources and registers. In this brief, we introduce a novel architecture with low resource utilization. A grouping algorithm is used to extract the common subexpressions (CS) of the encoding algorithm. Similar circuit structures are integrated through a two-layer architecture, which further reduces logical resources. For the special size of the generator’s matrix, we introduce a preprocessing method. In addition, configuration registers are used to replace the control unit. Implemented and verified on FPGA, the proposed architecture achieves a throughput of 4.69 Gbps using only 1658 LUTs and 1038 FFs. Compared with the previous architectures, this architecture achieves lower resource utilization and multi-Gbps throughput.

On the Construction of Multitype Quasi-Cyclic Low-Density Parity-Check Codes With Different Girth and Length

Multitype quasi-cyclic (QC) low-density parity-check (LDPC) codes are a class of protograph LDPC codes lifted cyclically from protographs with multiple edges, represented by two weight and slope matrices. For a given weight-matrix, an approach is proposed to find the maximum-achievable girth $g_{\max }$ of the corresponding multitype QC-LDPC codes by some inevitable chains having less complexity than the existing methods. This advantage leads to some new patterns of the weight matrices such that the corresponding codes have some improvements in terms of the maximum-achievable girths or the minimum-distance upper-bounds. In continue, for a given weight-matrix with maximum-achievable girth $g_{\max }$ , some slope-matrices are constructed by a depth-first search algorithm for which the corresponding multitype QC-LDPC codes with even girth $g$ , $g\le g_{\max }$ , have smaller lengths, higher rates, or larger minimum-distances than the state-of-the-art achievements. Simulation results show that the constructed codes have some error-rate advantages than PEG, random-like, CCSDS, and 802.11n/ac IEEE standard LDPC codes.

Edge coloring of graphs with applications in coding theory

In this paper, a new type of edge coloring of graphs together with an algorithm for such an edge coloring is presented to construct some column-weight three low-density parity-check (LDPC) codes whose Tanner graphs are free of 4-cycles. This kind of edge coloring is applied on some well-known classes of graphs such as complete graphs and complete bipartite graphs to generate some column-weight 3 LDPC codes having flexibility in terms of code length and rate. Interestingly, the constructed (3, k)-regular codes with regularities k = 4, 5,…, 22 have lengths n = 12, 20, 26, 35, 48, 57, 70, 88, 104, 117, 140, 155, 176, 204, 228, 247, 280, 301, 330, having minimum block length compared to the best known similar codes in the literature. In addition to linear complexity of generating such parity-check matrices, they can be considered as the base matrices of some quasi-cyclic (QC) LDPC codes with maximum achievable girth 18, which inherit the low-complexity encoder implementations of QC-LDPC codes. Simulation results show that the QC-LDPC codes with large girth lifted from the constructed base matrices have good performances and outperform random codes, progressive edge growth LDPC codes, some finite fields and group rings based QC-LDPC codes and also have a close competition to the standard IEEE 802. 16e (WiMAX) code.

Design of Nonbinary LDPC Cycle Codes with Large Girth from Circulants and Finite Fields

In this paper, we study a class of nonbinary LDPC (NBLDPC) codes whose parity‐check matrices have column weight 2, called NBLDPC cycle codes. We propose a design framework of (2, ρ)‐regular binary quasi‐cyclic (QC) LDPC codes and then construct NBLDPC cycle codes of large girth based on circulants and finite fields by randomly choosing the nonzero field elements in their parity‐check matrices. For enlarging the girth values, our approach is twofold. First, we give an exhaustive search of circulants with column/row weight ρ and design a masking matrix with good cycle distribution based on the edge‐node relation in undirected graphs. Second, according to the designed masking matrix, we construct the exponent matrix based on finite fields. The iterative decoding performances of the constructed codes on the additive white Gaussian noise (AWGN) channel are finally provided.

A Note on the Girth of (3, 19)-Regular Tanner’s Quasi-Cyclic LDPC Codes

In this article, we study the cycle structure of (3, 19)-regular Tanner’s quasi-cyclic (QC) LDPC codes with code length $19p$ , where $p$ is a prime and $p\equiv 1~(\bmod ~57)$ , and transform the conditions for the existence of cycles of lengths not more than 10 into polynomial equations in a 57th root of unity of the prime field $\mathbb {F}_{p}$ . By employing the Euclidean division algorithm to check whether these equations have solutions over the prime field $\mathbb {F}_{p}$ , the girth values of (3, 19)-regular Tanner’s QC-LDPC codes of code length $19p$ are determined. In order to show the good performance of this class of QC-LDPC codes, numerical results are also provided.

An FPGA-Based LDPC Decoder With Ultra-Long Codes for Continuous-Variable Quantum Key Distribution

In this paper, we propose a good decoding performance, low-complexity, and high-speed decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum-product decoding scheme. To reduce implementation complexity and hardware resource consumption, the messages in the iteration process are uniformly quantified and the function Ψ(x) is approximated with second-order functions. The decoder architecture improves the decoding throughput by using partial parallel and pipeline structures. A modified construction method of parity check matrices was applied to prevent read&write conflicts and achieve high-speed pipeline structure. The simulation results show that our decoder architecture has good performance at signal-to-noise ratios (SNRs) as low as -0.6 dB. We have implemented our decoder architecture on a Virtex-7 XC7VX690T field programmable gate array (FPGA) device. The implementation results show that the FPGA-based LDPC decoder can achieve throughputs of 108.64 Mb/s and 70.32 Mb/s at SNR of 1.0 dB when the code length is 262,144 and 349,952, respectively. The decoder can find useful applications in those scenarios that require very low SNRs and high throughputs, such as the information reconciliation of continuous-variable quantum key distribution.

Performance of Hybrid RF/FSO Cooperative Systems Based on Quasicyclic LDPC Codes and Space-Coupled LDPC Codes

Free space optical (FSO) communication systems provide wireless line of sight connectivity in the unlicensed spectrum, and wireless optical communication achieves higher data rates compared to their radio frequency (RF) counterparts. FSO systems are particularly attractive for last mile access problem by bridging fiber optic backbone connectivity to RF access networks. To cope with this practical deployment scenario, there has been increasing attention to the so-called dual-hop (RF/FSO) systems where RF transmission is used at a hop followed by FSO transmission to another. In this article, we study the performance of cooperative transmission systems using a mixed RF-FSO DF (decode and forward) relay using error-correcting codes including QC-LDPC codes at the relay level. The FSO link is modeled by the gamma-gamma distribution, and the RF link is modeled by the Additive White Gaussian Noise (AWGN) model. Another innovation in this article is the use of cooperative systems using a mixed FSO/RF DF relay using quasicyclic low-density parity check (QC-LDPC) codes at the relay level. We also use the space-coupled low-density parity check (SC-LDPC) codes on the same scheme to show its importance in cooperative optical transmission but also in hybrid RF/FSO transmission. The latter will be compared with QC-LDPC codes. The use of mixed RF/FSO cooperative transmission systems can improve the reliability and transmission of information in networks. The results demonstrate an improvement in the performance of the cooperative RF/FSO DF system based on QC-LDPC and SC-LDPC codes compared to RF/FSO systems without the use of codes, but also to the DF systems proposed in the existing literature.

Low Power QC-LDPC Decoder Based on Token Ring Architecture

The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

Structural Analysis of Nonbinary Cyclic and Quasi-Cyclic LDPC Codes with α-Multiplied Parity-Check Matrices

Structural Analysis of Nonbinary Cyclic and Quasi-Cyclic LDPC Codes with α-Multiplied Parity-Check Matrices

Impact of Correlated Fading on Multi-Connectivity

Multi-connectivity (MC) is regarded as one of the key features that meet the requirements of ultra-reliable low-latency communications for 5th generation networks, as it provides multiple diversity branches. Recently, we evaluated the decoding reliability of various MC setups and different combining algorithms by analyzing the resulting outage probabilities. In this work, we are interested in how much the performance is affected by correlated fading. Specifically, we analyze the outage probability of MC systems with joint decoding reception operating over correlated quasi-static Rayleigh and Nakagami-m fading channels. Our main contributions are as follows: (i) deriving the exact outage probability in integral form and the asymptotic outage probability at high signal-to-noise ratio (SNR) in closed form; (ii) deriving the correlation loss, which quantifies the extra SNR required under correlated fading as compared with the independent scenario; and (iii) evaluating frame-error rates of quasi-cyclic low-density parity-check codes by Monte-Carlo simulations. Our results show that the correlation loss is marginal for a low to moderate level of correlation, whereas the diversity gain is not affected by correlation whatsoever. Furthermore, we find that the correlation loss is independent of the degrees of freedom encapsulated by the Nakagami-m fading parameter.

Construction of Irregular Protograph-Based QC-LDPC Codes With Low Error Floor

In this article, we design finite-length irregular protograph-based quasi-cyclic (QC) low-density parity-check (LDPC) codes with good waterfall performance and low error floor. To achieve a low error floor, we eliminate a targeted set of dominant elementary trapping sets (ETS) ${\mathcal{ L}}$ in the Tanner graph of the code. For a given rate and girth, the codes are designed to be free of the largest set of problematic ETSs for a given block length, or to have the shortest block length while a given set of ETSs is avoided. The design is based on a search algorithm that identifies whether any instance of any structure within ${\mathcal{ L}}$ exists in the Tanner graph of the constructed code or not. The search algorithm performs this task with minimal complexity, making it feasible to construct practical codes by running the search algorithm a large number of times. Simulation results are provided to demonstrate the superior performance of designed codes compared to similar state-of-the-art irregular QC-LDPC codes.

Error Floor Estimation of QC-LDPC Coded Modulation With Importance Sampling

This letter presents a low-complexity error floors estimation method for bit-interleaved coded modulation with quasi-cyclic low-density parity-check (LDPC) codes. Using surrogate bit-channels (SBCs) as hypothetic equivalent channels, the importance sampling method based on the stable trapping sets is applied to evaluate the error floors. It is shown that the error floors of bit-interleaved coded modulation systems can be effectively estimated, and the presented method is appropriate for various types of modulators and interleavers.

High-throughput GPU layered decoder of quasi-cyclic multi-edge type low density parity check codes in continuous-variable quantum key distribution systems

The decoding throughput during post-processing is one of the major bottlenecks that occur in a continuous-variable quantum key distribution (CV-QKD) system. In this paper, we propose a layered decoder to decode quasi-cyclic multi-edge type LDPC (QC-MET-LDPC) codes using a graphics processing unit (GPU) in continuous-variable quantum key distribution (CV-QKD) systems. As described herein, we optimize the storage methods related to the parity check matrix, merge the sub-matrices which are unrelated, and decode multiple codewords in parallel on the GPU. Simulation results demonstrate that the average decoding speed of LDPC codes with three typical code rates, i.e., 0.1, 0.05 and 0.02, is up to 64.11 Mbits/s, 48.65 Mbits/s and 39.51 Mbits/s, respectively, when decoding 128 codewords of length {10}^{{6}} simultaneously without early termination.

Low Density Parity-Check Codes Based on Affine Permutation Matrices

Recently, Low Density Parity-Check (LDPC) codes based on Affine Permutation Matrices (APM) drew lots of attention. Compared with the Quasi-Cyclic LDPC (QC-LDPC) codes, these kinds of codes have some advantages. APM-LDPC codes obtain lower cycle-distributions, minimum hamming distance and greater girth. This paper explains the importance of cyclic distribution by comparing APM-LDPC codes with QC-LDPC codes. Then a particular form of APM-LDPC codes is proposed and researched. The new codes can low down the cycle-distribution to larger extent. In the following research, an effective method, which constructs the new codes with fixed girth, is proposed. Simulations show that the construction method is reasonable and effective. The transmission performances are better than the traditional methods, as well. Finally, the implementation and verification are carried out on FPGA.

Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware Utilization

Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%–109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.

A Joint Encryption, Channel Coding and Modulation Scheme Using QC-LDPC Lattice-Codes

We propose a new nonlinear Rao-Nam like symmetric key encryption scheme. In our design, we employ a specific type of coded modulation schemes namely quasi-cyclic low-density parity-check (QC-LDPC) lattice-codes which have low-complexity encoding and decoding algorithms. Due to the application of coded modulation schemes in our design, the proposed scheme performs encryption, encoding and modulation simultaneously. Therefore, we regard the proposed scheme as a joint cryptosystem . The proposed joint cryptosystem withstands all variants of chosen plaintext attacks applied on Rao-Nam like cryptosystems due to its nonlinearity. Moreover, some conditions implying the uniformity of the ciphertexts distribution are introduced through our analysis. Our scheme is efficient and admits small key size. These features are obtained due to several reasons including the quasi-cyclic form of the generator and the parity-check matrices of QC-LDPC lattice-codes, and the simple hardware structure for generating the permutation matrix, the intentional error vector and the nonlinear functions used in our design. The QC-LDPC lattice-codes facilitate high-rate transmission which is suitable for bandlimited AWGN channels. Our simulations indicate that QC-LDPC lattice-codes outperform the error performance of high-order coded modulation schemes based on QAM modulations. Hence, our scheme provides secure, reliable and efficient data transmission in bandlimited AWGN channels.