Abstract
In this paper, we propose a good decoding performance, low-complexity, and high-speed decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum-product decoding scheme. To reduce implementation complexity and hardware resource consumption, the messages in the iteration process are uniformly quantified and the function Ψ(x) is approximated with second-order functions. The decoder architecture improves the decoding throughput by using partial parallel and pipeline structures. A modified construction method of parity check matrices was applied to prevent read&write conflicts and achieve high-speed pipeline structure. The simulation results show that our decoder architecture has good performance at signal-to-noise ratios (SNRs) as low as -0.6 dB. We have implemented our decoder architecture on a Virtex-7 XC7VX690T field programmable gate array (FPGA) device. The implementation results show that the FPGA-based LDPC decoder can achieve throughputs of 108.64 Mb/s and 70.32 Mb/s at SNR of 1.0 dB when the code length is 262,144 and 349,952, respectively. The decoder can find useful applications in those scenarios that require very low SNRs and high throughputs, such as the information reconciliation of continuous-variable quantum key distribution.
Highlights
Low-density parity check (LDPC) codes, a class of forward error correction codes proposed by Gallager [1], have attracted extensive attentions over the past few decades
To evaluate our proposed scheme, the field programmable gate array (FPGA)-based LDPC decoder is implemented on a Xilinx VC709 evaluation board, which is populated with a Virtex-7 XC7VX690T FPGA with 433,200 look-up tables (LUTs), 866,400 FFs, 3,600 DSP slices, and 52,920 Kb Block RAMs (BRAMs)
In this paper, we have designed and implemented an FPGA-based LDPC decoder using the side information (SI)-layered belief propagation (LBP) algorithm that can achieve a better trade-off between the decoding performance and implementation complexity
Summary
Low-density parity check (LDPC) codes, a class of forward error correction codes proposed by Gallager [1], have attracted extensive attentions over the past few decades. Combining LDPC codes with the good decoding performance and FPGA devices with powerful parallel processing, we first proposed an FPGA-based LDPC decoder based on the side information (SI) [26] layered sum-product scheme to meet the needs of the CV QKD systems. Another key point we utilized to improve the decoding performance is to increase the code length above 200,000. This puts forward high demands on the hardware resource consumption.
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