Push-pull Output Stage Research Articles

Current Mirror Improved Potentiostat (CMIPot) for a Three Electrode Electrochemical Cell.

This work presents a novel compact CMOS potentiostat-designed circuit for an electrochemical cell. The proposed topology functions as a circuit interface, controlling the polarization of voltage signals at the sensor electrodes and facilitating current measurement during the oxidation-reduction process of an analyzed solution. The potentiostat, designed for CMOS technology, comprises a two-stage amplifier, two current mirror blocks coupled to this amplifier, and a CMOS push-pull output stage. The electrochemical method of cyclic voltammetry is employed, operating within a voltage range of ±0.8 V and scan rates of 10 mV/s, 25 mV/s, 100 mV/s, and 250 mV/s. The circuit is capable of reading currents ranging from 10 µA to 500 µA. Experimental results were obtained using a potassium ferrocyanide K3[Fe(CN)6] redox solution with concentrations of 10, 15, and 20 mmol/L, and their corresponding voltammograms were evaluated. The experimental results from a discrete circuit demonstrate that the proposed potentiostat topology produces outcomes consistent with those of classical topologies presented in the literature and industrial equipment.

A high-gain high-drive operational amplifier

Abstract This paper presents a high-gain, high-drive operational amplifier based on the 0.18 μm technology. The first stage employs a current-reuse common-source common-gate structure to enhance gain, while the second stage utilizes a transconductance-enhanced push-pull output stage. This design achieves high-drive performance while retaining a high gain. Simulation using Cadence software demonstrates that, under a 5 V power supply voltage, the amplifier exhibits a low-frequency gain of 120 dB, with output sink and source current capabilities reaching 17.7 mA and 2.53 mA, respectively.

16-channel photonic–electric co-designed silicon transmitter with ultra-low power consumption

A hybrid integrated 16-channel silicon transmitter based on co-designed photonic integrated circuits (PICs) and electrical chiplets is demonstrated. The driver in the 65 nm CMOS process employs the combination of a distributed architecture, two-tap feedforward equalization (FFE), and a push–pull output stage, exhibiting an estimated differential output swing of 4.0Vpp. The rms jitter of 2.0 ps is achieved at 50 Gb/s under nonreturn-to-zero on–off keying (NRZ-OOK) modulation. The PICs are fabricated on a standard silicon-on-insulator platform and consist of 16 parallel silicon dual-drive Mach–Zehnder modulators on a single chip. The chip-on-board co-packaged Si transmitter is constituted by the multichannel chiplets without any off-chip bias control, which significantly simplifies the system complexity. Experimentally, the open and clear optical eye diagrams of selected channels up to 50 Gb/s OOK with extinction ratios exceeding 3 dB are obtained without any digital signal processing. The power consumption of the Si transmitter with a high integration density featuring a throughput up to 800 Gb/s is only 5.35 pJ/bit, indicating a great potential for massively parallel terabit-scale optical interconnects for future hyperscale data centers and high-performance computing systems.

An area-efficient automotive LDO with scalable maximum load current exhibits excellent response to line and load transients

A compact LDO with scalable maximum load current is presented. A transconductor with multiple current outputs implements the error amplifier, as well as two feed-forward paths. A push-pull output stage is employed to drive the gate of the pass transistor. Zeros are created by the feed-forward paths, as well as by an RC network to realize an area- and power-effective frequency compensation, that ensures the LDO stability over a wide range of load currents and capacitances. The proposed LDO was implemented in a 0.13 µm CMOS process. The sizing strategy is presented in the paper, along with simulation and measurement results that validate the design. The LDO provides a stable 1 V output voltage when the input voltage varies between 1.2 V and 1.5 V, the load current varies between zero and 100 mA, and the load capacitance takes values between 100 nF and 10 µF. Its nominal quiescent current is just 9.6 µA while the die area is exceptionally small, only 0.0065 mm2. The integrated LDO exhibits excellent responses to load and line transients: when the load current jumps between 100 µA and 100 mA in 0.3 µs the measured output voltage overshoot and undershoot are below 3.6% of nominal value for CLOAD = 470 nF; the measured overshoot and undershoot caused by the line voltage jumping between 1.3 V and 1.5 V in 3 µs are smaller than 1.2% for the same CLOAD.

Optimization Possibilities for DC Current Transformer

The paper analyzes the consumption performance of DC current transformers based on linear class B, and half bridge classD compensation amplifiers, as well as self-oscillating flux gate current transformers based on push-pull and source–sink output stages.Compensation amplifiers, push-pull and source-sink output stages are used to generate feedback current in order to compensatemagnetic flux in the magnetic concentrator core, produced by electrical current flowing through a conductor under measurement. Thefocus of the analysis is the investigation of conditions for appearance of the bus-pumping effect to which all switching versions of DCcurrent transformers are prone. All sufficient conditions for bus pumping effect appearance are explained for the most critical case ofDC current measurement; the main issues are analyzed, giving better insight to power consumption, and possible hazards to DCcurrent transformer circuitry. It is highlighted the existence of particular exploitation conditions that lead to the state where the class Dbased DC transformers are inferior to conventional class B based counterparts. Finally, when a linear compensating amplifier isreplaced with a switching counterpart, it has been demonstrated that it is possible to expect a feasible improvement in energyconsumption in the middle of the ideal half-class D class and classical B class realisations.

OPERATION PRINCIPLE, ADVANCED PROCEDURES AND VALIDATION OF A NEW FLEX-SPI COMMUNICATION PROTOCOL FOR SMART IoT DEVICES

Abstract In this paper, we report on hardware structure, operation mode and software development for a new advanced communication protocol whose aim is obtaining a fully shared SPI bus with a fixed amount of wires, without renouncing to advantages of a push-pull output stage and obtaining an architecture capable of great flexibility. All four signals of a classic SPI protocol are entirely shared by the slaves on bus: when a master wants to communicate with a particular device, it will perform an addressing at packet level: starting from its main characteristics, various adopted solutions to realize a shared SPI bus will be analyzed, explaining how a communication session is performed. The firmware structure was designed as a software stack composed by interacting layers, tracing model of similar protocols that share with FlexSPI some features. Some of the advanced procedures that can be performed thanks to this protocol will be discussed, highlighting the suitability of FlexSPI for dynamic smart objects; in fact, by adding these features to developed framework, it is possible to explore and appreciate expandability of this communication protocol, making it suitable to meet advanced IoT requirements of smart objects. FlexSPI can be built like a MAC layer above the SPI bus, to process all necessary pieces of information to perform the packet level addressing, using a stack having a layered architecture. This is idea followed in the firmware development, to implement this communication protocol, experimentally verified in the performed and reported communication tests, confirming that it is possible to obtain a shared push-pull bus.

FRAMEWORK IMPLEMENTATION, FIRMWARE DEVELOPMENT AND CHARACTERIZATION OF FLEX-SPI COMMUNICATION PROTOCOL: ENERGY CONSUMPTION ANALYSIS AND COMPARISON WITH I2C STANDARD

Abstract In this paper, we report a detailed description of developed Flex-SPI firmware structure together with experimental tests carried out by using ad-hoc instrumental setups based on TI MSP- EXP430F5438 experimenter boards. Developed framework, aimed to provide a solid base to test the possibility of performing a shared SPI communication with a fixed number of wires without renouncing to push-pull output stage advantages, has been implemented and successfully validated. Also, FlexSPI energy consumption has been evaluated and then compared with the I2C one, by proper experimental setups and related data processing: the two protocols, in fact, share several features, although they rely on a different hardware configuration. The energy/bit metric was chosen so that the two output stages can be compared regardless the effective quantity of exchanged packets; thus, this measure provides an indication of necessary energy amount to move a single bit to guarantee the correct firmware functionality. Despite larger quantity of exchanged data due to channel reservation needs (with a 35% traffic overhead, in the performed tests), the FlexSPI total energy consumption is comparable with the I2C one, at the same communication speed; thus a lower energy/bit requirement is required for FlexSPI protocol, decreasing with the negotiated speed, in this way proving FlexSPI protocol as a suited and valid choice for high-speed low-consumption communications inside embedded systems with a developed architecture capable of great flexibility.

Analysis and Design Procedure of a Novel Low Power Highly Linear Operational Transconductance Amplifier

In this paper, a new highly linear operational transconductance amplifier (OTA) is presented. Proposed OTA employs two linearization techniques of cross-coupled double differential pairs and resistive source degeneration to achieve highly linear response under low power consumption. Considering the linearity and the frequency response issues as main parameters of OTA in the communication circuits, design procedure is theoretically formulated for the best linearity and optimum frequency compensation. Proposed OTA is simulated in 0.18-μm TSMC CMOS technology by Hspice simulator. While, the power consumption is only 467 μW, applying two-tone input voltage with amplitude of 0.6 Vp-p at 10 MHz frequency results in -61 dB third-order intermodulation (IM3) distortion of the output current that still remains below -44 dB for amplitudes up to 1 Vp-p. A precise frequency response analysis is performed which has resulted in optimum values of resistor and capacitor for miller compensation. Using common mode feedback in both stages and push-pull based output stage lead to 108 dB CMRR at DC that decreases to 84.5 dB at 100 kHz frequency.

A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS

This paper details a duplex architecture coupled with a linear Class-AB push-pull output stage that maximizes the power efficiency of linear wideband drivers for high-speed transceivers. The duplex driver merges transmission, reception, and termination; eliminates hybrid and termination overhead; and enables adaptive echo cancellation and rail-to-rail full-duplex operation. Implemented in 28 nm CMOS, this GPHY driver passes the 1000BASE-T and 100BASE-TX compliance tests using a 2.5 V supply and meets the transmit specifications for the half-duplex 10BASE-T Ethernet using a 3.3 V supply.

A 1.2-V 90-nm Fully Integrated Compact CMOS Linear Power Amplifier Using the Coupled L-Shape Concentric Vortical Transformer

This paper presents a 90-nm fully integrated CMOS linear power amplifier (PA) using a coupled L-shape concentric vortical transformer (CL-CVT) for the fourth-generation long-term evolution (LTE) communication standard. Using the proposed output combining CL-CVT architecture, the outer diameter required by the power combiner is reduced by 66% compared to the distributed active transformer with similar performance. Moreover, the PA is able to efficiently combine four push-pull output stages and achieve nearly constant power over several LTE bands with a total chip area less than 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With a 1.2-V supply voltage, the PA delivers 27.3-dBm maximum output power with a peak drain efficiency of 47% at 2.4 GHz. Using a 20-MHz LTE 16-QAM test signal, the PA achieves 24.6% power-added efficiency at an output power level of 22 dBm and passes the spectral requirements defined by the LTE standard without using any pre-distortion or calibration techniques.

Fast‐transient capacitor‐less low‐dropout regulator with assistant push‐pull output stage using bootstrap technique

An output-capacitor-less low-dropout regulator (LDR) with an assistant push-pull output stage using a bootstrap technique is proposed. By utilising such a technique, the proposed LDR is able to achieve a fast-transient response. The proposed LDR was implemented in a standard 0.35 μm CMOS process. Measurement results show that the undershoot of the output voltage is 375 mV at the condition of the load current switching from 1 to 200 mA at a rise time of 500 ns.

Power Efficient Class AB Op-Amps With High and Symmetrical Slew Rate

Various class AB two-stage op-amps with high and approximately symmetrical slew rate and very simple architecture are introduced in this brief. A current replicating branch with scaled-down transistors in combination with adaptive loads is used to implement a push-pull output stage with maximum output current several times higher than the bias current. Postlayout simulation and measurement results are presented and verify a 400%-500% slew rate and 80%-100% GB enhancement with only 5% additional quiescent power dissipation and 20% silicon area increase.

High-Performance LC Resonant Amplifier Design and Implementation

The work mainly by the front level attenuator, the LC tuned amplifier, the push-pull output stage is composed. The first level weakens 40dB fixedly through pi the attenuator realization. Front the double grid field effect manages 3SK223 to make the level to increase the controllable LC tuned amplifier, the LC resonance by double harmonious and the list harmonious cascade way, enhanced the system selectivity. The complete machine gain is bigger than the 80dB, AGC control area to achieve above 60dB.The output stage uses the low pressure high electric current high speed axle to the axle structure integration operational amplifier OPA2354 push-pull transformer coupling output, sharpened the belt load capacity greatly. In order to reduce the amplifier as far as possible the noise and ceases the high frequency auto excitation, this design has adopted the power source filter, the shield, electromagnetic compatibility, the interstate coupling, the impedance matching and so on many kinds of measures. After the test, this plan has completed completely the basic function and the expansion function. Sweeps the frequency source turning on input end after CPLD self-made DDS, May very convenient see the system frequency response on the oscilloscope.

A 4H Silicon Carbide Gate Buffer for Integrated Power Systems

A gate buffer fabricated in a 2-μm 4H silicon carbide (SiC) process is presented. The circuit is composed of an input buffer stage with a push-pull output stage, and is fabricated using enhancement mode N-channel FETs in a process optimized for SiC power switching devices. Simulation and measurement results of the fabricated gate buffer are presented and compared for operation at various voltage supply levels, with a capacitive load of 2 nF. Details of the design including layout specifics, simulation results, and directions for future improvement of this buffer are presented. In addition, plans for its incorporation into an isolated high-side/low-side gate-driver architecture, fully integrated with power switching devices in a SiC process, are briefly discussed. This letter represents the first reported MOSFET-based gate buffer fabricated in 4H SiC.

A High-Speed and High-Linearity BiCMOS Optically Coupled Isolation Amplifier

To improve the current non-linear optically coupled isolation amplifier and high power consumption, we designed a low-power, high-speed and high-linearity BiCMOS optically isolation amplifier. There are only two push-pull output stages configuration bipolar transistor (BJT) in the design process, the rest of the circuit is the CMOS device. To improve amplifier gain linearity and stability, we introduce the complementary symmetrical photodiode, in the optically coupled part and every amplifier, negative feedback is introduced. Experimental results indicate that the design of optically isolation amplifier ± 3 dB bandwidth increases 40 kHz than optically isolation amplifier ISO100 bipolar, When the power supply voltage is 4.8 V, the delay - power product of DP is lower than ISO100 37.3 pJ, gain linearity is up to 5.5 × 10-5, which is suitable for high-speed control system.

HIGH-SLEW RATE LOW-QUIESCENT CURRENT RAIL-TO-RAIL CMOS BUFFER AMPLIFIER FOR FLAT PANEL DISPLAYS

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.

A Rail-to-Rail Class-B Buffer With DC Level-Shifting Current Mirror and Distributed Miller Compensation for LCD Column Drivers

A rail-to-rail class-B buffer with a dc level-shifting current mirror and the proposed distributed Miller compensation is presented for liquid crystal display (LCD) column drivers. By using a dc level-shifting current mirror, the rail-to-rail input stage directly turns on/off the rail-to-rail push-pull output stage without extra comparators. It results in a low-power rail-to-rail class-B buffer. By utilizing the distributed Miller compensation, this class-B buffer achieves the high stability and the fast transient response over a wide-range capacitance load. The class-B buffer is fabricated in a 0.35 μm CMOS process, and its die area is 122 μm × 54 μm. From the experimental results, the measured quiescent current is 3 μA and the settling time for a rail-to-rail full swing to settle within 0.2% of the final voltage for both rising and falling edges is 1.78 μs under a load capacitance of 1200 pF with a power supply of 3.3 V.

Dual Active-Capacitive-Feedback Compensation for Low-Power Large-Capacitive-Load Three-Stage Amplifiers

A dual active-capacitive-feedback compensation (DACFC) scheme for low-power three-stage amplifiers with large capacitive loads is presented in this paper. Dual high-speed active-capacitive-feedback paths enable the non-dominant complex poles of the amplifier to be located at high frequencies for bandwidth extension under low-power condition. The proposed DACFC amplifier also consists of two left-half-plane (LHP) zeros that relax the stability criteria for further improving the gain-bandwidth product (GBW) and reducing the required compensation capacitance of the amplifier. Moreover, the transient response of the DACFC amplifier is enhanced via the use of the small compensation capacitance and the presence of push-pull second and output stages.

A rail-to-rail unity gain buffer amplifier for low-cost high resolution TFT LCD panels

A structural rail-to-rail high voltage CMOS buffer amplifier for driving gamma correction reference voltage of TFT LCD panels is presented. It operates from a single supply and only consumes 0.5 mA at 18 V power supply voltage. The circuit is designed for 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5 mA static current and 1 kohm resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50 mV at 5 mA constant output current, and below 2.5 mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and an input level detector using hysteresis comparator are applied. The complete circuit is realized in a high voltage 0.18 um 18 V CMOS process technology for display driver IC and the area measures only 0.056 mm2. The circuit operates at supply voltages from 8 V to 18 V.

A novel on-chip high to low voltage power conversion circuit

A novel power supply transform technique for high voltage IC based on the TSMC 0.6 μm BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm2 area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/°C. Compared with the traditional LDO (low dropout) regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.