Punchthrough Stopper Research Articles

Device characteristics of MOSFETs with self‐aligned punch‐through stopper structure

AbstractSelf‐aligned punch‐through stopper (SPS) MOSFETs are made using high energy ion implantation; punch‐through stopper (PTS) layers are formed after gate electrode delineation. The SPS structure features: 1) a retrograded PTS layer with a gradually increasing impurity profile; and 2) a relatively lower impurity concentration around the source and drain region. These characteristics of the PTS structure permit both junction capacitance reduction and adjustment of threshold voltage (Vth) (specifically, a reduced Vth and suppressed reverse short‐channel effect) and improved current drivability, short‐channel characteristics, and hot‐carrier immunity. The proposed structure is also effective in reducing process steps because only one implantation is needed to adjust the profile.

A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance

An asymmetrical n-MOSFET device structure was developed that is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micrometer level without reduction of the supply voltage below 3.5 V. In this structure, large-tilt implantation is used to form the gate-overlapped LDD (GOLD) region at the drain electrode only. A halo (punchthrough stopper) is used at the source, but not at the drain. Superior hot carrier reliability and high punchthrough resistance are obtained using this device structure. A reliability-limited supply voltage of 4.2 V is obtained for an asymmetrical n-MOSFET with effective channel lengths as short as 0.25 mu m. By extrapolation from the measured threshold roll-off characteristics, the authors expect that this structure can be designed with substantially shorter channel length while maintaining the 3.5-V supply voltage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Atomic layer doped field-effect transistor fabricated using Si molecular beam epitaxy

Atomic layer doped field-effect transistors (ALD FETs) have been fabricated, in which n-type, δ-doped, and p-type doped regions are used as a conductive channel and a punchthrough stopper, respectively. It is shown that the ALD FET shows a high transconductance while the punchthrough current is sufficiently suppressed, indicating that the device is promising as a short-channel FET for the next generation of ultralarge scale integration.

A new p-channel MOSFET with large-tilt-angle implanted punchthrough stopper (LATIPS)

A buried-channel p-MOSFET with a large-tile-angle implanted punchthrough stopper (LATIPS) is described. In this device the n/sup +/ LATIPS region was successfully realized adjacent to the p/sup +/ source/drain, even without a sidewall spacer, by taking advantage of the n/sup +/ large-tilt-angle implant. In spite of the relatively deep p/sup +/ junction of 0.2- mu m depth and the low n-well concentration of 1*10/sup 16/ cm/sup -3/, the 0.5- mu m LATIPS device (with corresponding channel length of 0.3 mu m) achieved high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/decade with a high transconductance of 135 mS/mm. >

Computer simulation of a new MESFET with an atomic-layer-doped structure

A new MESFET structure is proposed, utilizing atomic-layer-doping (ALD) technologies. The MESFET is constructed with both n- and p-type ALD regions: one is designed as a conducting channel and the other as a punchthrough stopper. Assuming Si ALD-MESFETs, the superiority of the threshold voltage dependence on gate length is clearly demonstrated by two-dimensional computer simulation. The threshold voltage can remain constant even in the half-micrometer range. When the punchthrough stopper is omitted from the device (which is then called a delta-FET), punch-through phenomena dominate the FET operation within the range of several micrometers, and the threshold voltage decreases sharply in that range. An optimum design concept for ALD-MESFETs using computer simulation is also discussed. When doping conditions are appropriately designed, the transconductance value can be increased slightly, over that of delta-FETs. ALD devices widen the application field of digital doping technologies using MBE and are candidates for developing half- or quarter-micrometer range devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Improved planar isolation with buried-channel MOS FET's

A potential VLSI MOS device called BGP (buried-channel graded-drain with punchthrough stopper) with planar isolation is characterized in terms of fabrication techniques and its device performance. This planar isolation approach has been realized using highly directional dry etching and through-field-oxide implantation. It features simultaneous formation of punchthrough and parasitic channel stoppers and an effective channel width almost equivalent to nominal one. Fundamental device characteristics such as short-channel and narrow-channel effects are investigated. Good isolation performances are demonstrated in devices having 1μm feature size at standard 5V operation.

Characteristics of a buried-channel graded drain with punchthrough stopper (BGP) MOS device

MOS device structures having a graded-drain (G), a buried-channel (B), and a punchthrough stopper (P) are realized by a triimplantation technique without additional masking. Combined effects of B, G, and P are experimentally investigated. Significant improvements in source-to-drain (S-D) breakdown voltage and the short-channel effect are observed in a BGP device. The BGP device structure will be durable for 5-V operation in the coming VLSI era.

Characteristics of a Buried-Channel Graded Drain with Punchthrough Stopper (BGP) MOS Device

MOS device stuctures having a graded-drain (G), a buried-channel (B), and a punchthrough stopper (P) are realized by a tri-implantation technique without additional masking. Combined effects of B, G, and P are experimentally investigated. Significant improve ments in source-to-drain (S-D) breakdown voltage and the short-channel effect are observed in a BGP device. The BGP device structure will be durable for 5-V operation in the coming VLSI era.