Pulse Width Distortion Research Articles

A Study of Interpolation Compensation Based Large Step Simulation of PWM Converters

Real-time online simulation based on a real-time workshop (RTW) plays a vital role in the study and application of power electronics. However, restricted by the performance of equipment and hardware, the simulators so far available in the market mainly support simulation steps over 50 μs, while large step simulation may result in the action delay of pulse-width modulating (PWM), numerical oscillation and high-level non-characteristic harmonic distortion. In view of these problems, this paper puts forward a modeling method based on integral prediction and interpolation compensation. First of all, prediction is performed one step in advance by the implicit trapezoidal method to find out the accurate time when the triangle carrier wave intersects with the modulation wave. At the same time, a mathematic model is built for the insulated gate bipolar transistor (IGBT) to output equivalent voltage waveform according to the principle of area equivalent. Next, in MATLAB/Simulink, offline simulation is performed with the three-phase AC-DC-AC converter as the subject. By comparing the control accuracy, the content of harmonic wave and the simulation time, the simulation effects of the 50 μs fixed-step interpolation prediction model are the same as that for a 5 μs fixed-step standard model. Finally, the effectiveness and high efficiency of this algorithm are verified on a real-time simulator, marking the application of offline models on real-time simulators.

Silicon photonic switch-based optical equalization for mitigating pulsewidth distortion.

Optical transmitters typically require electrical pre-amplification using driver amplifiers to optimize the optical modulation depth. To enhance the detection sensitivity and optimize the overall link budget, equalization is required to compensate for undesired signal distortion induced by the transmitter. In this paper, we propose and demonstrate a novel optical equalization scheme using a silicon photonic micro-ring resonator (MRR)-based switching circuit for mitigating driver-amplifier-induced pulsewidth distortion. The switching circuit simultaneously functions as a spatial optical switch as well as a two-stage optical bandpass filter for optical equalization. The experimental results indicate a 4.5-dB detection sensitivity enhancement at a data rate of 12.5 Gbits/s. The proposed approach is robust to different levels of pulsewidth distortion without additional signal processing, and has possibilities to support higher data rates by adjusting the MRR parameters.

Optical Transmitter Based on a 1.3-μm VCSEL and a SiGe Driver Circuit for Short-Reach Applications and Beyond

Long-wavelength vertical-cavity surface-emitting lasers (LW-VCSELs) with emission wavelength in the 1.3-μm region for intensity modulation (IM)/direct detection optical transmissions enable longer fiber reach compared to C-band VCSELs, thanks to the extremely low chromatic dispersion impact at that wavelength. A lot of effort has been recently dedicated to novel cavity designs in order to enhance LW-VCSELs' modulation bandwidth to allow higher data rates. Another approach to further improve VCSEL-based IM speed consists of making use of dedicated driver circuits implementing feedforward equalization (FFE). In this paper, we present a transmitter assembly incorporating a four-channel 0.13-μm SiGe driver circuit wire-bonded to a novel dual 1.3-μm VCSEL array. The short-cavity indium phosphide buried tunnel junction VCSEL design minimizes both the photon lifetime and the device parasitic currents. The integrated driver circuit requires 2.5-V supply voltage only due to the implementation of a pseudobalanced regulator; it includes a two-tap asymmetric FFE, where magnitude, sign, relative delay, and pulse width distortion of the taps can be modified. Through the proposed transmitter, standard single-mode fiber reach of 20 and 4.5 km, respectively, for 28- and 40-Gb/s data rate has been demonstrated with state-of-the-art power consumption. Transmitter performance has been analyzed through pseudorandom bit sequences of both 2 7 -1 and 2 31 -1 length, and the additional benefit due to the use of the driver circuit has been discussed in detail. A final comparison with state-of-the-art VCSEL drivers is also includedt.

On the Gaussian Pulse Propagation Through Multilayer Graphene Plasmonic Waveguides—Impact of Electrostatic Screening and Frequency Dispersion on Group Velocity and Pulse Distortion

In this paper, we analytically describe the characteristics of propagating and diffusive plasma waves in multilayer graphene heterostructures targeted toward implementing on-chip interconnects. When the effect of collision-dominated resistance of the graphene sheet is negligible, the plasma waves propagate through the media without pulse reshaping. However, in the presence of electron scatterings due to phonons and charged impurities in the sample, the plasma waves acquire a diffusive character and undergo significant frequency-dependent pulse reshaping. We analytically model the propagation speed and pulse-width distortion of a narrow-band Gaussian signal centered at THz frequencies by accounting for the finite electrostatic screening between the multiple layers of graphene. The consequences of signal distortion and attentuation on limiting the signal bit-rate and the impact on energy dissipation are quantified. A partition length of the plasmonic waveguide that distinguishes between $LC$ - and $RC$ -dominated regimes of signal transport is derived. For on-chip interconnect application, the upper bound on the propagation length of plasma waves is determined by both the energy dissipation and the bit-rate requirement of the interconnect infrastructure. Upon comparison with on-chip electrical interconnects, we identify the energy budget that can be allocated toward plasmonic transceivers, such that the overall plasmonic communication is more energy efficient compared to electrical communication.

5 Gb/s 2:1 fully-integrated full-rate multiplexer with on-chip clock generation circuit in 0.18-μm CMOS

A 5 Gb/s 2:1 full-rate multiplexer (MUX) has been designed and fabricated in SMIC 0.18-μm CMOS process. A clock generation circuit (CGC) is also integrated to provide the MUX with both 2.5 and 5-GHz clock signals. The CGC is realized by a clock and data recovery (CDR) loop with a divide-by-2 frequency divider embedded in, where the two required clocks are obtained after and before the divider, respectively. In addition, the phase relation between data and clock is assured automatically by CDR feedback loop and the precise layout. The whole chip area is 812 × 675 μm, including pads. At a single supply voltage of 1.8 V, the total power consumption is 162 mW with an input sensitivity of <25 mV and a single-ended output swing of above 300 mV. And due to the full-rate architecture, the pulse width distortion (PWD) with multiplexed data is removed. The measured results also show that the circuit can work reliably at any input data rate between 2.46 and 2.9 Gb/s without need for external components, reference clock, or manual phase alignment between data and clock.

Pulsed-Latch Aware Placement for Timing-Integrity Optimization

Utilizing pulsed-latches in circuit designs is one emerging solution to timing improvements. Pulsed-latches, driven by a brief clock signal generated from pulse generators, possess superior design parameters over flip-flops. If the pulse generator and pulsed-latches are not placed properly, however, pulse-width degradations at pulsed-latches and thus timing violations might occur. In this paper, we present a unified placement framework for pulsed-latches to maintain the timing integrity. Our new placer has the following distinguished features: 1) a multilevel analytical placement framework to effectively prevent the potential pulse-width distortion problem; 2) a physical-location aware pulse-generator insertion algorithm to identify each desired group of a pulse generator and latches; and 3) a new optimization gradient for global placement to consider the impact of load capacitance of generators. Experimental results show that our placement flow can effectively consider pulse-width integrity and thus achieve much smaller total/worst negative slacks with marginal wirelength overheads, compared to a leading commercial and an academic placement flows.

A Second-Order Feedforward Optical Power Control Scheme for Automotive VCSEL Drivers

This letter presents a feedforward optical power control scheme for automotive 150-Mb/s vertical-cavity surface-emitting laser (VCSEL) transmitters. The bias current exhibits a second-order dependence upon temperature, while the modulation current is provided with a piecewise linear compensation of temperature variations. The resulting VCSEL modulation performance was analyzed in detail and experimentally validated. Over the harsh automotive temperature range from -40°C to 105°C, a high extinction ratio was maintained despite very tight tolerances on pulsewidth distortion (PWD); the variation of the emitted optical power was measured to be less than 1.2 dB, while maintaining an extinction ratio better than 12 dB and a PWD less than ±2%.

Statistical Model for Polarization Mode Dispersion in Single Mode Fibers

As the bit rate of fiber optic transmission systems is increased to more than , the system will suffer from an important random phenomena, which is called polarization mode dispersion. This phenomenon contributes effectively to: increasing pulse width, power decreasing, time jittering, and shape distortion. The time jittering means that the pulse center will shift to left or right. So that, time jittering leads to interference between neighboring pulses. On the other hand, increasing bit period will prevent the possibility of sending high rates. In this paper, an accurate mathematical analysis to increase the rates of transmission, which contain all physical random variables that contribute to determine the transmission rates, is presented. Thereafter, new mathematical expressions for: pulse power, peak power, time jittering, pulse width, and power penalty are derived. On the basis of these formulas, one can choose a certain operating values to reduce or prevent the effects of polarization mode dispersion.

A 1.25 Gb/s laser diode driver with pulse width optimization

A 1.25 Gb/s laser diode driver (LDD) with pulse width optimization has been implemented in a 0.6-μm BiCMOS process. This paper illustrates the relation between the pulse width distortion (PWD) of the output eye diagram and the driving amplitude from the second pre-amplifier. Also, a specific current setting circuit working together with an LDD is proposed to generate the optimum driving amplitude and to avoid device nonlinearity, temperature variation and process deviation. The measured results show a maximum crossing deviation of −3% and indicate the desired independence and stability.

82.5 Gsample/s (10.3125 GHz × 8 phase clocks) burst-mode CDR for 10G-EPON systems

A high-speed 82.5 Gsample/s sampling IC and its incorporated burst-mode CDR compliant for 10G-EPON systems are presented. The 82.5 Gsample/s sampling CDR successfully achieved a high pulsewidth distortion tolerance of more than plusmn0.53 UI under the distorted optical burst packets received condition of BER =1 times 10 -3 .

A CMOS optical receiver with subtraction-based level shifter for high-definition digital audio interfaces

This paper proposes a cost-effective CMOS optical receiver with a level shifter to reduce pulse width distortion and design complexity in high-definition digital audio interfaces. In this design, a level shifter is introduced at the receiver, in order to improve digital audio quality by threshold convergence. Measurement results demonstrate that the implemented optical receiver in a 0.25-μm CMOS technology can successfully reduce pulse width distortion within ?2% and circuit complexity.

An automatic threshold-converged CMOS optical receiver for high-definition digital audio interfaces

This paper proposes an automatic threshold converged CMOS optical receiver employing a threshold convergence technique to reduce pulse width distortion and design complexity in high-definition digital audio interfaces. A threshold concentrator is introduced at the receiver, in order to improve digital audio quality by aligning various logic thresholds of the input signals into a constant one. Simulation results demonstrate that the designed optical receiver in a 0.18-µm CMOS technology can successfully reduce pulse width distortion within -2% and circuit complexity.

System Penalty From Second-Order PMD Approximation: Reference Frame Implication

In this paper, we show that second-order PMD approximations, when derived using the input frame and output frame of an optical link, result in two different PMD systems represented by two distinct Jones matrices. In contrast to an all-order representation of a system, which is independent of reference frame, it is found that a finite second-order approximation cannot be obtained simultaneously in both input and output reference frames, except in some limited special cases. The consequences of this are illustrated by analyzing the difference between these two approximations in pulsewidth distortion. It is shown that the second-order PMD approximation in the input frame corresponds to a truncated second-order expansion of the pulse distortion, whereas the second-order PMD approximation in the output frame leads to an infinite-order pulse distortion

A Burst-Mode Bit-Synchronization IC With Large Tolerance for Pulse-Width Distortion for Gigabit Ethernet PON

A burst-mode bit-synchronization IC applied to the upstream transmission in a gigabit Ethernet passive optical network (PON) was experimentally verified to have a large tolerance for pulse-width distortion within <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$pm$</tex> 0.66 UI. The extra tolerance of 0.22 UI over the IEEE 802.3ah specification can be assigned to additional distortion generated at an optical receiver incorporated into an optical line terminal. Such a large tolerance was attained by precisely generated eight-phase clocks based on theoretical analyses of distortion tolerance considering real circuit parameters and by an enhanced data selector incorporating a pulse-width detector to monitor the pulse-widths of isolated bits. The IC developed includes a burst into series transformer to permit connection to commercially available PON LSI developed for serial data transmission in Ethernet systems. The theoretical study into the numbers of allowable bit errors and consecutive pattern matches in byte synchronization established following two conditions: 1) allowable error more than one bit in synchronization pattern with 10-bit length was required to hold the synchronization loss rate to less than a few times per year and 2) consecutive pattern matching more than twice was required to hold the synchronization error rate to less than a few times per year.

A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON

In this paper, we present an integrated 155-Mb/s burst-mode receiver (BMR) for passive optical network (PON) applications. The chip has been designed to receive optical signals over a wide dynamic range (-30 to -8 dBm) and temperature range (-40/spl deg/C to +85/spl deg/C). The chip was implemented using a 0.8-/spl mu/m 35-GHz SiGe BiCMOS technology and occupies an area of 4.3/spl times/4.9 mm/sup 2/ with a power consumption of 500 mW from a supply voltage of 5 V (3.3 V for the digital PECL output). In the receiver analog front end, we used a low-noise wide-band transimpedance amplifier followed by a nonlinear gain stage to cover a wide signal range without changing the transimpedance gain. The circuit dynamically adjusts the receiver threshold voltage through a feedback loop, thus optimizing the pulsewidth distortion and canceling the optical as well as the electrical offset voltages.

Pulsewidth distortion monitoring in a 40-Gb/s optical system affected by PMD

A novel technique for monitoring the pulse broadening due to polarization-mode dispersion (PMD) in optical systems is described. The technique is based on the measurement of the Stokes vectors at different frequencies over the spectrum of the received optical pulse find does not require a priori knowledge of the fiber PMD statistics or details of the optical path. The validity of our technique has been demonstrated by both simulation and experimental results.

On the second-order approximation of PMD

A second-order polarization mode dispersion (PMD) approximation based upon the pulse-width distortion has been studied. It shows that a complete second-order approximation should include the second derivative of the PR-ID vector as well as the first derivative of the PMD vector. Second-order pulse distortions are explicitly expressed including a 'first-order' term involving principal states of polarization (PSP) of the pulse and a second-order term involving the beating between fiber chromatic dispersion and effective PMD chromatic dispersion. An analytical result is derived for the probability of second-order PR-ID power penalty. It shows that the mean PMD of the fiber should be restricted to 26 ps and 18 ps, respectively for an optical link with zero and 850 ps/nm chromatic dispersion, in order to maintain a one dB second-order PMD power penalty with a probability below 10/sup -6/ at a data rate of 10 Gb/s. The analysis also indicates that a second-order PMD compensator can be used as a dynamic chromatic dispersion compensator.

A low-cost high-performance optical interconnect

Summary form only given. The optical waveguides have a uniformity of 1 dB. The resulting optical links have a jitter of no more than 150 ps not including pulse-width distortion, static skew between channels of less than 200 ps and dissipate 1.5 W. A representative multichannel eye pattern at 400 Mbit/s is shown. In this presentation we focus on the design approach and subsystem requirements that make this performance possible without sacrificing manufacturability or cost.

ELECTRONICS FOR HIGH SPEED, BURST MODE OPTICAL COMMUNICATIONS

Electronics for burst mode data communication over an optical data link will contribute to wider acceptance of photonic technology. This paper describes the concepts and difficulties inherent in burst mode optical communication systems, and proposes a new solution employing an ultra-high speed, high accuracy peak detector. Sensitivity penalties associated with this technique are reviewed. The method was implemented in an optical receiver with dc to 500 Mb/s operation, and at 200 Mb/s, demonstrates an isolated pulse sensitivity of −29.5 dBm, and pulse width distortion less than lns. An example application, the Multiple channel Optical Data LINK (MODLINK), is described: a fully dc-coupled, 12 parallel channel digital data link system designed for high speed optical fiber communication at bit rates ranging from dc to 200 Mb/s per channel, applicable at distances of centimeters to over 3 km.

Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS

A general procedure to size an inverter which drives a given capacitance load and which has precise pull-up and pull-down delays is discussed. This procedure is an iterative combination of a Newton-Raphson numerical method used to size the transistors, and ADVICE simulations to extract parameters used in the delay model for the inverter. The numerical method makes it possible to satisfy the delay constraints precisely, while ADVICE simulations ensure accuracy. This device-sizing procedure is then used to determine the sizes of inverters in two paths, one consisting of two inverters and the other three, each driving an arbitrary capacitive load, such that the complementary output of the two paths has minimal skew and pulsewidth distortion irrespective of the processing variations. A fully automatic procedure to achieve this requires only four ADVICE simulations and takes about four minutes of CPU time on an AMDAHL-5870 computer. The circuit designed by this procedure also has a very small skew and pulsewidth distortion with temperature variation with V/sub DD/ variation, and with the input rise and fall-time variations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>