Since Boff, Moll, and Shen’s discovery of the high-speed switching effect inherent in initially forward-biased silicon diodes that are suddenly reverse-biased in 1960 [1]; DSRD’s (as termed by Grekhov and Kardo-Sysoev in 1985 [2]) performance has not increased as their deep-diffusion manufacturing process remains the same as it was over 60 years ago. Albeit new pulse generator topologies which utilize diodes like DSRDs, i.e., SOS diodes (termed by Rukin in 1992 [3]) have shown improvement at circuit level given they operate under a higher direct-current density compared to that of DSRD-based pulsers – the voltage-to-risetime, dV/dt, of these silicon-based solid-state diodes remain on the order of 1012 V/s. Furthermore, all possible ways to improve pulse performance of DSRD made by deep diffusion have been extensively investigated and exhausted. To achieve the 1013 V/s (10 kV/ns) voltage-to-risetime required by an all-solid-state pulse generation utilized to support of the missions, improving DSRD manufacturing techniques must ensue.The process flow is schematically illustrated by Fig. 1. On starting degenerate doped wafer, two epitaxial layers are grown, first n- then p-type doped thus forming p-n junction of the diode.The doping profile is controlled by changing dopant flow into epi chamber. It allows getting an optimal diode doping profile predicted by simulation. Notice, the old diffusion process allows only predetermined doping profile (complementary error function) which is not optimal.After forming the blanket p-n junction structure on entire wafers, individual diode dies are separated by wafer patterning. Though the wafers remain intact. This is opposite to the old process where the wafers were cut into individual diode dies. In our technology, V-grooves are formed by anisotropic etching process resulting in structure shown on Fig. 2. Squares surrounded by the v-grooves will become diodes, Inner slopes of v-grooves become side walls of the diodes. Notice, in old technology side walls were usually vertical, which creates a weak point for electrical breakdown: it is limited by surfacee breakdown properties, not bulk silicon properties.Next is diode side surface insulation. It is achieved by thermal oxidation. Thus, the diodes get the best surface passivation (i.e., thermal SiO2). The p-n junction is located near middle of the V-groove slope. Thus, there is no local spike of electric field where avalanche breakdown starts. Eventually, the breakdown properties of this diode are much closer to bulk silicon limit – as compared to old technology where the breakdown was surface limited.At next stage the silicon dioxide layer is removed on top surface but remains on v-groove slopes. Now we have wafers with diode arrays, terminated and passivated by side surfaces.Further, selective electroplating of copper is performed to form electrical contacts. Also, it is a step in preparation to wafer stacking. In old technology, metallization was at much earlier stage of flow and thus it interfered with side insulation. In selective electroplating, copper is deposited only on silicon surfaces, and does not deposit on SiO2 surfaces of v-groove insulation.To finish preparation for wafer bonding, tin is selectively deposited over copper. Then, wafers are aligned and stacked. The wafer stack is heated above tin melting temperature. By solid-liquid interdiffusion, Cu/Sn intermetallic compound is formed. It has much higher melting point compared to tin. Bonding process continues until entire tin layer is consumed.Now the bonded wafer stack is ready for last step in the processing – cutting into stacked DSRDs. The cutting is regular mechanical sawing. The saw lines are along the lines of v-grove bottoms.The process and resulting device design are patented [4].On next step of this project, electrical performance of final stacked DSRDs will be compared to performance of stacked DSRDs manufactured by traditional deep diffusion-based technology. Boff, A., J. Moll, and R. Shen. "A new high-speed effect in solid-state diodes." in 1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 3, pp. 50-51. IEEE, 1960. Grekhov, I. V., V. M. Efanov, A. F. Kardo-Sysoev, and S. V. Shenderey. "Power drift step recovery diodes (DSRD)." Solid-State Electronics 28, no. 6 (1985): 597-599..Rukin, S. N. "Pulsed power technology based on semiconductor opening switches: A review." Review of Scientific Instruments 91, no. 1 (2020): 011501.Bellinger, A.Caruso, A.Usenko, US Patent Application “Stacked Diode with Side Passivation and Method of Making the Same” filed 09/10/2021. Figure 1
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Jan 1, 2023
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