Pulse Width Modulation Method Research Articles

BLDC Motor Drives with A Programmable Simplified C-Block to Generate Accurate Six-Step PWM Based on STM32 Microcontroller

This paper presents a digital implementation of a brushless direct current motor (BLDCM) drive with a six-step pulse width modulation (PWM) using a programmable simplified C-block based on the STM32 microcontroller. The implementation is conducted through the PSIM simulation platform, which is commonly used for power electronics and motor control. This approach combines the benefits of using a programmable simplified C-block for precise and flexible programming with the PWM concepts of the STM32 microcontroller. The PWM method used on the BLDCM drive is the unipolar upper PWM technique (H~PWM_L~ON). The performance of the PWM implementation is analyzed in detail, including the accuracy of the PWM generation using a Fast Fourier Transform (FFT), the gating of the IGBTs in the three-phase inverter, and the effect of the duty cycle on the BLDCM's speed, phase voltage, and phase current.

An Improved Phase-Disposition Pulse Width Modulation Method for Hybrid Modular Multilevel Converter

The hybrid modular multilevel converter (MMC) consisting of half-bridge submodules (HBSMs) and full-bridge submodules (FBSMs) is a promising solution for overhead lines high-voltage direct current systems (HVDC) due to the advantages of direct current short circuit fault ride-through (DC-FRT) capability. This paper proposes an improved phase-disposition pulse width modulation (PDPWM) method for the hybrid modular multilevel converter. The number of carriers can be reduced from 3N (N is the number of submodules in each arm) to 6. The theoretical harmonic analysis of the improved PDPWM method for hybrid MMC is performed by using double Fourier integral analysis. The influence of three carrier displacement angles between HBSMs and FBSMs in the upper and lower arms on harmonic characteristics is investigated. The output voltage harmonics minimization PDPWM scheme and circulating current harmonics cancellation PDPWM scheme can be achieved by selecting the optimum carrier displacement angles, respectively. The proposed method for hybrid MMC is verified by the simulation and experimental results.

A simplified space vector pulse width modulation method for a three‐level four‐leg inverter considering the neutral point potential balance

AbstractThis paper presents a simple three‐dimensional space vector modulation method in ghγ coordinates for a three‐level four‐leg neutral‐point‐clamped inverter. The idea uses redundant vectors as centre points to establish two‐level space vector diagrams simplifying the original space, the first sector of which is designated as subspaces, where a modulation process is implemented. The duty cycle and all possible switching sequences in a tetrahedron can be calculated automatically without manual storage and can avoid a full‐scale search process. Additionally, the neutral point potential can be balanced by three types of charge through cancellation. Such features enable the inverter to demonstrate good performance under closed‐loop control. Moreover, the proposed method can be applied to a multilevel inverter. Simulation and experimental results demonstrate the effectiveness of the proposed concept.

Selection of PWM Methods for Common-Mode Voltage and DC-Link Capacitor Current Reduction of Three-Phase VSI

This paper evaluates several important pulse-width modulation (PWM) methods developed to reduce the common-mode voltage (CMV) or DC-link capacitor current (DCC) of two-level three-phase voltage source inverter (VSI) in motor drive applications. In addition, a PWM selection criterion is introduced to properly utilize these advanced PWM methods in the VSI system. In the motor drive systems, the high CMV generates the large common-mode current, which may cause electromagnetic emissions and motor damages. Also, the large DCC may have an adverse effect on the life expectancy and increase the volume of DC-link capacitor. Therefore, reducing the CMV and DCC is required in modern VSI systems. So far, various PWM methods have been studied to reduce these CMV and DCC. However, they need to be fairly compared and evaluated together under the same condition to provide information so that power electronics engineers can select the appropriate PWM method when designing their motor drive systems. In this paper, the principle of these PWM methods is reviewed and their performance is analytically evaluated. Then, the PWM selection criterion is described based on the comprehensive evaluation studies. Lastly, the simulation and experimental results with an interior permanent magnet synchronous motor (IPMSM) drive system are presented to validate the presented PWM selection criterion.

Monitoring and control of the protection system of electric drives with the method of pulse-width modulation

This article deals with increasing the stability of power supply by improving the protection and control of electric drives using the pulsewidth modulation (PWM) method. The method consists in the formation of periodic series of pulses of a certain duty cycle, creating separately positive and negative half-waves of the current sinusoid in the motor windings. The PWM method of base vectors (vector modulation) consists in switching between several pre-selected states of the inverter, each of which corresponds to a certain spatial position of the resulting voltage vector applied to the engine. In the PWM method, each phase zone is divided into 3 subzones with its own duty cycle. This method is suitable for both three-stage inverter and six-stage inverter. It can be seen in the work that the quality of the resulting current depends not only on the number of subzones for the formation of base vectors, but also on the number of voltage pulses per subzone. The more pulses fall on the formation subzone, the cleaner the resulting current curve is.

Decentralized space vector pulse width modulation method for multilevel single-phase half bridge converters

This study presents a space vector pulse width modulation (PWM) method for a multilevel single-phase decentralized power converter (DPC) called MSPDPC. The proposed model is built by connecting half-bridge cells in series. The output voltage can be adjusted according to demand by adding or subtracting cells. Cells use communication protocols to transmit and receive information with two neighboring cells. The received data contains information for the decentralized space vector pulse width modulation (DSVPWM) method proposed in this paper. In the proposed DSVPWM method, cells set up links to exchange information such as cell position, total cells in a phase, reference voltage amplitude, and reference frequency. The PWM control signals of each cell are calculated based on the information received. The study also focuses on evaluating the ability to adjust the switching vector and the corresponding dwell time of the cells when the structure of the DPC changes. The ability to dynamically reconfigure the DPC is a crucial feature that ensures uninterrupted power supply in case of one or several cell failures. The system automatically establishes a new state with the active cells. The proposed configuration and communication method between cells provide very fast configuration times. The load voltage of the DPC is adjusted to 0.5 times the voltage per cell, which allows the modulation voltage amplitude to be adjusted best according to the load requirements. The study used Matlab/Simulink software to review the initial assessments. The proposed model and algorithms will be verified on the Digital Signal Processor (DSP) platform with a 220V/500W load.

Control of Distributed Generation Using Non-Sinusoidal Pulse Width Modulation

The islanded mode is one of the connection modes of the grid distributed generation resources. In this study, a distributed generation resource is connected to linear and nonlinear loads via a three-phase inverter where a control method needing no current sensors or compensator elements is applied to the distribute generation system in the islanded mode. This control method has two main loops in each phase. The first loop controls the voltage control loops that adjust the three-phase point of common coupling, the amplitude of the non-sinusoidal reference waveform and the near-state pulse width modulation (NSPWM) method. The next loop compensatesthe harmonic compensator loop that calculates the voltage harmonics of the point of common coupling in each phase, and injects them to compensate the non-sinusoidal reference waveforms of each phase. The simulation results in MATLAB/SIMULINK show that this method can generate balanced three-phase sinusoidal voltage with an acceptable total harmonic distortion (THD) at the joint connection point.

Design of Depth-Focused Electromagnetic Transmitting Scheme Based on MFSPWM Method

Aiming at the frequency-domain electromagnetic method (FEM) detection system, a depth-focused transmitting scheme based on multi-frequency sinusoidal pulse width modulation (MFSPWM) method is proposed to solve the problems of low exploration efficiency in conventional single-frequency transmitting scheme and low vertical resolution in 2n multi-frequency pseudo-random (MFPR) transmitting scheme. Depending on the target depth range and required measurement accuracy, a depth-focused waveform is designed to focus the excitation field energy on a narrow frequency band. In this article, the principle of MFSPWM method is theoretically analyzed and the expression of depth-focused waveform is derived by Fourier analysis. Then, the parameter optimization of the main frequencies is performed for the desired spectrum. Further, simulations and experimental tests were carried out to verify the feasibility and effectiveness of the proposed scheme. The results show that the proposed scheme has better spectral features with multiple closely spaced frequencies and less undesired harmonics, which ensures high vertical resolution for the specific depth target. After parameter optimization, the peak-to-peak value of the current waveform was reduced by about 40% and the effective signal of the high-frequency component was increased by about 20%. The forward simulation and field test results show that the proposed scheme has higher detection accuracy and interference resistance for the specific depth target compared to the MFPR scheme.

A Complete Online Solution of Harmonic Elimination PWM Method Using Modified-Equilibrium Optimizer-Levenberg- Marquardt Algorithm

This paper proposes a novel online solution, i.e. Modified-Equilibrium Optimizer-Levenberg-Marquardt (M-EO-LM) algorithm, for the symmetric and asymmetric harmonic elimination pulse width modulation (HEPWM) methods of the modular multilevel cascaded converters. A detailed comparison of the proposed M-EO-LM algorithm with nine state-of-the-art algorithms is also presented for twenty-nine unimodal, multimodal and composite benchmark test functions. M-EO-LM has proven its effectiveness by outperforming these algorithms. EO algorithm is first introduced for the solution of HEPWM method. Its comparison with several state-of-the-art algorithms depicts its superiority; but it gets stuck in the local minima. Modified-EO (M-EO) solves the problem by enhancing its exploration ability, and is then attached to a rapid calculus-based LM method to form the novel M-EO-LM algorithm. M-EO-LM algorithm initiates the solution process by solving the HEPWM equations for nine angles ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N=9$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.78\leq M\leq 6.86$ </tex-math></inline-formula> ) offline in only two iterations, depicting its remarkable convergence ability. Solution angles are then divided into several groups, serving as the search space for the online M-EO-LM algorithm. A comparison between HEPWM and nearest level modulation methods based on the output voltage THD values is provided to report the maximum number of solvable HEPWM angles for a complete online solution. These angles ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N=8$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.78\leq M&lt; 5.18$ </tex-math></inline-formula> ) are then solved online using the M-EO-LM algorithm. Comparing the computational times of the proposed online algorithm with differential evolution-Newton Raphson algorithm proves the rapid solution behavior of the M-EO-LM algorithm, validated through the simulation and real-time experimental results.

Per-Phase Analysis, Efficient Implementation and Performance Evaluation of a 24-Sector Discontinuous PWM for Split-Phase Induction Motor Drives

Space vector-based 24-sector pulse width modulation (PWM) techniques for split-phase induction motor (SPIM) drive offer better performance than the 12-sector PWM methods; however, these methods are complex to implement. This paper analyses a space vector based 24-sector discontinuous PWM from a per-phase perspective. Analysis of three-phase average pole voltages, pertaining to this method, shows that each phase is clamped for a 60 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> interval in each half cycle, which is divided into three sub-intervals of 15 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> , 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> and 15 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> , respectively. The common-mode voltage is shown to be related to the fundamental voltage of one of the phases in each sector and to that of different phases in different sectors. This analysis leads to an understanding of the offset voltages to be added to the two sets of three-phase sinusoidal modulating signals for generating the equivalent modulating signals for the two inverters driving the SPIM. Further analysis of the switching sequences suggests appropriate carrier waves for the modulating signals to be compared against. The computationally efficient implementation of the 24-sector discontinuous PWM (DPWM-1), thus developed, is validated on a 6-kW laboratory prototype SPIM drive. Stator flux ripple-based analysis is used to evaluate stator current distortion and rms torque ripple of different PWM techniques. Simulated instantaneous torque ripple and torque harmonic spectra of the different techniques are compared. The proposed method offers lower THD at high speeds and lower switching loss at high power factors than the 24-sector continuous space vector PWM with significantly low computational effort.

Harmonic mitigation in a hybrid system using intelligent control methods

The demand for electrical energy is increasing day by day. Therefore, renewable energy systems are used in the power system. Due to the intermittent nature of renewable sources, hybrid systems are developed. This paper presents a cascaded multilevel inverter fed with hybrid DC (Direct Current) sources. The pulses to the switches of the proposed inverter are obtained using the sinusoidal pulse width modulation method. An intelligent control method for the regulation of the output voltage of the inverter is implemented. The performance of the intelligent control strategy is compared with that of the conventional PI (Proportional Integral) controller. Furthermore, the proposed system is compared with the existing works. The simulation and experimental results show that the proposed controller outperforms well by providing a voltage and current THD (Total Harmonic Distortion) of 4.13% and 0.93%, respectively, which are within the IEEE (Institute of Electrical and Electronics Engineers) 519-2014 standard.

Driving Asynchronous Induction Launchers: Design and Simulation of a Novel Power Conditioner with a Brief Review

The design and implementation of an asynchronous coilgun’s structure is relatively simple compared with other types of linear induction launchers. In order to drive rotating electrical machines, multilevel converter structures have attracted much attention in recent decades as a result of their unique advantages. A linear induction launcher has an identical theoretical background to rotating electrical machines; therefore, multilevel converter structures can be applied to them as well. The stator of a launcher can be excited by generators or capacitor groups whose voltage and frequency might be fixed or changeable by a power conditioner. The aim of this study is to design and simulate a novel power conditioner as a multilevel converter topology for the power source of an asynchronous coilgun. Cascaded H-Bridge multilevel converter topology constitutes the proposed power conditioner in which a level-shifted pulse-width modulation method is used to generate appropriate pulses for the power switches of the converter. Additionally, variable-voltage variable-frequency control is involved in the converter’s modulation.

Advanced PWM Techniques for Multi-Level Inverters With a Multi-Level Active CM Noise Filter

Pulsewidth modulation (PWM)-based power electronics inverters are being widely used for various applications, including motor drives. However, the common-mode voltage (CMV) resulting from switching operations in the PWM inverters causes significant performance degradation of the system and can cause potential damage to motors. Since the effects of the CMV can be more severe in wide bandgap (WBG) and high switching frequency-based converter systems, various methods have been proposed to mitigate the CM noise issues. This work presents a multi-level inverter system composed of a multi-level inverter with a proposed multi-level active power filter (APF). For attenuating the CMV in multi-level inverters using multi-carrier-based PWM methods, a novel PWM method is presented for the proposed multi-level APF. The three-phase five-level active-neutral-point-clamped (ANPC) II-type inverter using the apparent switching frequency doubling (ASFD) PWM is used as an example of the multi-level inverters and carrier-based PWM methods to analyze and verify the proposed CMV attenuation method. The APF generates and injects the APF voltage equal to the CMV to attenuate the CM noise accurately. Various key challenges, including the dead-time compensation, are addressed through the proposed advanced PWM techniques to improve the CMV attenuation performance. Simulation and experimental results are provided to verify the comparison and effectiveness of the proposed CMV attenuation method.

A Modified DPWM Method With Minimal Line Current Ripple and Zero-Sequence Circulating Current for Two Parallel Interleaved 2L-VSIs

High-performance comprehensive optimization of line current ripple, zero-sequence circulating current (ZSCC), and switching losses is a challenge for parallel interleaved inverters. This article proposes a modified discontinuous pulse width modulation (PWM) method for two parallel interleaved two-level voltage-source inverters (2L-VSIs), which are regarded as a single 3L-VSI to optimize its vector sequence. The line current ripple is the priority optimization target to guarantee the principle of the nearest three vectors is applied in each subsector. To reduce the ZSCC and switching losses, the vector combinations with smaller changing rate of ZSCC are selected, and the phase-leg carrying the highest current is clamped. The detailed design procedure of 3L-vector sequence and how to distribute to 2L-VSIs are revealed. The quantitative performance comparison between the proposed PWM method and existing ones in terms of line current ripple, ZSCC, and switching losses are made. Experimental results confirm the effectiveness of the proposed method.

An Improved PWM Method of Five-Leg VSI Fed Dual-PMSM System With Duty Cycles Regulation

The five-leg voltage source inverter dual motors system has been widely studied in recent years for its advantage of fewer power switching devices. The traditional modulation method generates the voltage vectors needed by the two motors alternately in one control period, in which active voltage vectors of one motor can operate for a short time thus limit the speed ranges of the two motors. Regarding the deficiency, the relationship between the basic active voltage vectors of the two motors is futher analyzed and an improved pulsewidth modulation (PWM) method is proposed in this article, by which the duty cycles of five-phase PWM signals are modified as a whole. Under the premise that the common leg pulse width meets the requirements of the two motors in one control period, the effective time of the active voltage vectors of the two motors is tremendously expanded with no hardware added, and the speed ranges of the two motors are thus greatly expanded. When one motor runs at a relatively low speed, the speed range of the other motor can be effectively expanded with this method, compared with the traditional one. Simulations and experiments also verify the accuracy of the theoretical analysis and the feasibility of the proposed method.

Optimized Multi-Carrier PWM Strategy and Topology Review for Multi-Cell Series-Parallel Medium-Voltage Rectifier

Solid-state transformer (SST) acting as a medium-voltage (MV) rectifier is a viable solution to supply low-voltage DC (LVDC) loads directly from the MV ac grid. Different from a classical boost-derived power-factor-correction (PFC) topology, the multicell series-parallel (MCSP) converter steps down and distributes the input ac voltage by multiple switching cells while providing the PFC function. We propose an optimized multicarrier pulsewidth modulation (PWM) strategy to avoid unwanted modes by modified multicarrier waveforms for ensuring frequent parallel connectivity to improve balancing effect while preserving simple current control implementation. Compared with conventional phase-shifted (PS) PWM and other modified multilevel carrier methods, the proposed method has no adverse effect on the input current distortion and optimizes the balancing effect on the capacitor voltages resulting suppressed circulating currents. Effectively reduced current stresses on the switch devices could lead a reduction of conduction loss on the device. Topology discussion, circulating currents, digital implementation, and loss analysis are provided. Finally, the superiority of the proposed PWM method is validated by thermal-based simulation presenting a power loss breakdown and comparing with other PWM methods. A full-scale prototype is developed, and the experimental outcomes verify the remarkable performance of proposed PWM scheme in balanced and even suppressed switch currents with improved system efficiency.

An Improved DPWM Method for Single-Phase Five-Level ANPC Converters With Switching Loss Reduction and Capacitor Voltage Balance

Neutral-point (NP) voltage and flying capacitor (FC) voltage balance, and power loss reduction are important guarantees for the stable and high-efficiency operation of single-phase five-level active neutral-point clamped (5L-ANPC) converters. However, little reports about capacitor voltage balancing with the power loss reduction have been proposed for single-phase 5L-ANPC converters. In order to obtain the above merits, an improved discontinuous pulsewidth modulation (DPWM) method with capacitor voltage balance and power loss reduction is proposed. First, an optimized common-mode voltage is injected into the modulation waves to decrease the switching loss in each switching period. In particular, the calculation of the injected common-mode voltage is based on the analysis of the deviation of the NP voltage. Hence, a fast-dynamic response of the real-time NP voltage controlling is acquired in the meantime. Besides, in order to balance the FC voltage, the weight factors of NP voltage deviation and FC voltage deviation are compared to generate the selecting signals of redundant switching states. As a result, the capacitor voltage balance and power loss reduction are realized simultaneously. Finally, the simulation and experimental results validate the correctness and feasibility of the proposed DPWM method.

Carrier Redistribution Pulsewidth Modulation for Five-Level Stacked Multicell Converter

This article presents a modified carrier redistribution pulsewidth modulation (CRPWM) method for the five-level stacked multicell converter (SMC). The proposed CRPWM method is modified by exchanging the arrangement of the carriers of phase disposition pulsewidth modulation (PDPWM). With the ingenious carrier arrangement, the proposed PWM technique equalizes the utilization of phase leg voltage redundancies corresponding to the charging and the discharging state of each floating capacitor during one switching period of all the switches. The proposed modulation strategy has the same harmonic performance of line-to-line voltage with PDPWM, while the switch utilization is the same as phase-shifted pulsewidth modulation (PSPWM). Therefore, the voltage balancing of floating capacitors is achieved during a minimum switching period even with the influence of load current change and inappropriate carrier ratio is considered. The modified CRPWM is analyzed in theory and the voltage balancing ability and output harmonics performance are compared with PSPWM and traditional CRPWM. Simulation and experimental results on the laboratory prototype five-level SMC confirm the validity of the proposed CRPWM technique.

Investigation of Staggered PWM Scheme for AC Common Mode Current Minimization in SiC-Based Three-Phase Inverters

The advent of SiC devices which results in lower rise times and steep <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{d}v/\text{d}t$ </tex-math></inline-formula> at the inverter terminal can compromise the common mode (CM)-conducted emissions’ compliance, motor peak ac -CM currents, and leakage currents. Consequently, this results in a high ac and dc side CM filter weight. AC filters at the inverter output terminal are effective in reducing the slew rate of inverter voltage thereby reducing the peak CM current. However, a special case with high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{d}v/\text{d}t$ </tex-math></inline-formula> arising from low duty cycles is found to increase the peak ac-CM current significantly. Reduced CM voltage (CMV) schemes are popular pulsewidth modulation (PWM) methods to minimize the peak CMV but suffer from high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{d}v/\text{d}t$ </tex-math></inline-formula> under this special case as well. In this article, a staggered PWM scheme to minimize such peak ac -CM currents for a high-speed variable frequency drive (VFD) is evaluated using a three-level SiC-based T-type inverter as a demonstrator. From the analysis, the proposed switching pattern shows benefits over conventional sinusoidal PWM (SPWM) scheme and is found to be scalable to other PWM schemes and voltage levels. Simulation and experimental results are shown to validate the performance of the proposed switching pattern.

New PWM Strategy to Enable Dual-Mode Operation Capability in Common-Grounded Transformerless Inverters

A novel pulsewidth modulation (PWM) technique has been presented in this article, which enables the converter to operate in the conventional (boost) mode as well as in the buck mode (proposed). The proposed buck PWM method significantly reduces the current stresses of the components compared to the boost mode. Using this combined modulation technique, a dual-mode operation of such a class of inverters is demonstrated to accommodate a wide input voltage variation while maintaining the regulation of the output ac voltage. The proposed modulation technique is simple to implement and has been implemented in some of the conventional Type-I and Type-II inverters to demonstrate a very wide input voltage range (200–400 V dc), while keeping a fixed output voltage of 110 V ac rms. The theoretical analysis, key operating circuit, and waveforms are presented along with the thermal profile of various switches. Experimental results show that Type-I and Type-II inverters rated at 500 VA have around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$95.5~\pm ~1$ </tex-math></inline-formula> % efficiency for a wide load range with a peak efficiency of 97.3% in buck * invert mode for Type-I and 95.5% for Type-II inverters.