Pseudo NMOS Logic Research Articles

Design of High Performance and Power Efficient Flash ADC

In this paper, Flash Analog to digital converter is implemented. The designed Flash ADC consists of a resistive ladder network, comparators, the thermometer to a binary encoder and the entire design is carried out using Tanner tools employing 180nm technology. The reference voltage applied to the resistive ladder network is 1.8V. A two-stage operational amplifier is used as a comparator in the flash ADC. Here, we are modifying the structure of operational Amplifier using Power Gating Technique. Binary code is obtained from the thermometer code by utilizing a Mux based encoder by designing the MUX in domino Logic. The major problem that usually appears in flash ADC is as the number of resolution bits increases, the Area, as well as the power consumption of the circuit, also increases. In this paper, we principally concentrated to lessen the propagation delay of the ADC by optimizing encoder circuitry. With the purpose of reducing latency, Encoder is implemented using 2:1 mux based on Pseudo NMOS Logic. Performance parameters of Flash ADC such as delay as well as average power are calculated and compared.

Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems

Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to a large number of Trellis transitions. However, high constraint length is necessary to improve the accuracy of the decoding process for the high rate convolution code. In particular, the Add-Compare-Select (ACS) module of the Viterbi Decoder will have large numbers of trellis states and trellis transitions with increased constraint lengths, which give rise to high hardware complexity and large power consumption. As the performance of the Viterbi decoder mainly depends on its efficient implementation of the ACS module, in the literature, several methods are presented for the implementation of ACS for the Viterbi decoder. The methods based on Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer, Shannon’s decomposition circuits, body-biased pseudo-NMOS logic and Quasi Delay Insensitive (QDI) timing model performance is analyzed. The methods are implemented using CMOS technology. In this paper, FinFET and CNTFET-based ACS implementation is performed. From the analysis, it has been found that the Carbon Nanotube-based implementation is better in performance when compared to the CMOS and FinFET technology. The proposed QDI model and retiming circuits for ACS block operate above 1[Formula: see text]GHz with high driving current and low power.

Area Efficient Modified Array Multiplier

Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

32-bit Kogge-Stone based Hybrid Adder Implemented using Standard Cells of Different Logic Families

Adders performs a critical role in all computational operations, thereby optimizing them with respect to design constraints for a system is essential. In this paper, standard cells of different logic families, namely- CMOS, Pseudo NMOS, and MGDI, are designed in Cadence Design Suite Virtuoso 6.1.7 in 180nm technology and characterized using Liberate 15.1.3. The standard cell libraries thus created are then applied to 32-bit KSA (Kogge-Stone Adder) and KSA based proposed hybrid adder that are implemented in Verilog, functionally verified on Xilinx Vivado 2020.2 and synthesized on Cadence Genus 15.22. Pseudo NMOS logic shows 14.03% area savings and MGDI offers 54.43% power saving based on area per cell over the traditional CMOS technology. It is also seen that the proposed adder offers a decrease in power and delay by 32.13% and 13.75% over KSA, respectively, in CMOS logic. Further discussions are made and suitable applications for all designs are also discussed.

WITHDRAWN: Parametric analysis of schematic for efficient sub-system design with MOSFET’s scaling factors

Abstract Integrated Circuits (IC) focus on low power devices, as per the demand in industries. In VLSI circuits, for modern applications, power dissipation is an essential constraint as it plays a crucial role in the system’s overall performance estimation. Many techniques, like power gating or clock gating, can be used to reduce unnecessary power consumption. Non-working parts would be switched off during the non-functional period. IC designers are still facing the problem of choosing the best logic among different styles for the set of user-defined constraints. It is easy to select the optimal, with the prior availability of metrics, to make the design efficient. In this paper, the analysis was done on Mentor Graphics EDA Tool with 130nm technology to predict the characterization of given logic with multiple scaling factors and tested through distinct voltages by continuously changing MOSFET dimensions. The clocked CMOS is like CMOS in some conditions at the cost of power dissipation (196.49uW in CCMOS and 100.24nW in CMOS). Pseudo nMOS is suffering from delay variations (with 117.97pS to 503.74 pS) by changing MOS size and input voltage in their characteristics, unlike CMOS logic. It is to notice that the CMOS and clocked CMOS logics are ideal in maintaining constant delays in response to change in FET dimensions or supply voltages. Similarly, pseudo-NMOS logic, otherwise, is a delightful choice to use (with an average power maximum of 108.54 nW) when a constant power dissipation is mandatory from the system even, it’s far operated in vibrant conditions. Identified efficient schematic which is either essential to arrive the most effective sub-system, which in turn increases the overall system performance.

A novel area efficient on-chip RO-Sensor for recycled IC detection

Out of different types of counterfeit integrated circuits (ICs) present in the supply chain, recycled ICs are major threat to security and reliability of electronic components. Recycled ICs possess shorter lifetime and it is extremely difficult to distinguish a recycled IC in a group of fresh IC with similar functionality. Out of several recycled IC detection methodology, Ring Oscillator (RO) sensor based detection approach is most efficient, because of its simple design and can detect ICs used only for few days. In this paper, we proposed two different types of modified RO sensor with lower area overhead. First RO sensor accelerates the aging to improve the detection of recycled ICs which are used for few days. The second architecture uses current controlled configurable RO (C-CRO) to further improve the detection of recycled IC. The RO in both the proposed sensor is designed by using modified pseudo NMOS logic based inverter. The proposed inverter accelerates the aging caused by negative bias temperature instability (NBTI) and lower the impact of process variation (PV) to improve the rate of detection. Both the proposed RO sensors are simulated in 90 nm CMOS technology. The simulation result shows both the proposed sensor improves the rate of detection as compared to the conventional sensor.

Improved low power implicit pulse triggered flip-flop with reduced power dissipation

In this paper, an improved implicit pulse triggered flip-flop is proposed based on conditional pulse enhancement scheme. The pass transistor logic AND gate creates a faster discharge path. Then a conditional pulse enhancement scheme is used in order to conditionally enhance the pulse only when required. This avoids unnecessary switching action in the flip-flop. Then in order to reduce the power dissipation further, the pseudo NMOS logic is replaced with a NAND gate structure. This reduces the static power consumption and as well as the switching power consumption. Thus results in an overall power saving. The results are obtained in 180 nm CMOS technology using mentor graphics. The results are compared with four conventional flip-flops and its power saving is improved.

Improved low power implicit pulse triggered flip-flop with reduced power dissipation

In this paper, an improved implicit pulse triggered flip-flop is proposed based on conditional pulse enhancement scheme. The pass transistor logic AND gate creates a faster discharge path. Then a conditional pulse enhancement scheme is used in order to conditionally enhance the pulse only when required. This avoids unnecessary switching action in the flip-flop. Then in order to reduce the power dissipation further, the pseudo NMOS logic is replaced with a NAND gate structure. This reduces the static power consumption and as well as the switching power consumption. Thus results in an overall power saving. The results are obtained in 180 nm CMOS technology using mentor graphics. The results are compared with four conventional flip-flops and its power saving is improved.

Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique With Pseudo NMOS and Transmission Gate Logics

Abstract Comparatorare most widely used second electronic components after operational amplifier. For ADC circuit we have to use the high speed and low power consumption based comparator. SVL circuit is used tom reduce the offset voltage which requires high voltage gain. A SVL circuit can supply maximum DC voltage to an active load circuit on request or can decrease the DC voltage supplied to a load circuit in the standby mode was developed. SVL circuit is used with comparator which reduce the power consumption from 258.6μw to 156.7μw. Pseudo nmos logic and transmission gate logic is used with the SVL based current comparator which further reduce the power consumption in the standby mode. This technique based comparator is fabricated on the tanner tool of 45nm technology.SVL technique is mostly recommended for CMOS logic.

Efficient adders for assistive devices

The Body sensor network [IEEE 802.15] is a wireless communication network consisting of assistive devices which are of prime importance in medical applications. The delay critical and power hungry blocks in these assistive devices are designed so that they consume less power, have low latency and require a lesser area on chip. In this paper, we present a qualitative as well as a quantitative analysis of an asynchronous pipelined adder design with two latest computation completion sensing approaches based on Pseudo NMOS logic and other based on C-element. The Pseudo NMOS based completion sensing approach provides a maximum improvement of 76.92% in critical path delay at supply voltage of 1.2V and the maximum drop in power dissipation has been observed at a supply voltage of 1.1V which is 85.60% as compared to C-element based completion sensing approach. Even at low voltages such as 0.8V, there is a significant improvement in speed and power which is 75.64% and 74.79% respectively. Since the adder is the most widely used component in all present day assistive devices, this analysis acts as a pointer for the application of asynchronous pipelined circuits with efficient Pseudo NMOS based completion sensing approach in low voltage/low power rehabilitative devices.

Resistive MOSFET brain-inspired threshold logic gates

The concept of a pseudo-resistive threshold logic circuit that uses a combination of CMOS inverter and bulk driven MOSFET pseudo-resistive divider circuit for designing a universal NOR gate is presented. Inspired from the neuronal firing mechanisms, the inverter implements the binary threshold decision, while pseudo-resistive circuit provides the summation of normalised weighted inputs. The proposed logic gate when tested using the TSMC 0.18 µm low voltage process show an overall improved performances in terms of area, delay and power in comparison with CMOS and pseudo NMOS logic.

A comparative analysis of power and delay optimise digital logic families for high performance system design

In this paper, we propose a high performance system design methodology taking the best average delay on prime. Our analysis method is based on the commonly used logical effort methodology, extended to the least delay to find the transistors sizing. Simulation results are tabulated using SPECTRE in 0.18 µm CMOS technology as applied to three different logic styles including static CMOS, pseudo-NMOS and skewed logic. We observe that NAND based pseudo-NMOS logic design having NMOS width as 1 µm exhibits least delay but with enormous power dissipation, evaluated by the tool, whereas, skewed logic style response is better in terms of total power. Thus, the method used accurately shows the trade-off in power-delay of a given circuit, allowing a designer to choose the most appropriate logic style.

Design and Analysis of Conventional and Ratioed Cmos Logic Circuit

This paper compares the ratioed logic circuits and conventional CMOS design. This comparison performed on efficient CMOS circuit realizations and the ratioed logic circuits and it is resulted in to superiority of ratioed circuit over the conventional CMOS in some cases with respect to area, input capacitance. In this paper, 4-input NAND gate is designed using the conventional CMOS design and pseudoNMOS logic design, which is the most common form of CMOS ratioed logic and the results are compared using Microwind and DSCH2 CMOS layout tools.

PMIC용 고신뢰성 eFuse OTP 메모리 설계

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip`s BCD process, and the layout size is ($

전기적 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로 설계

본 논문에서는 전기적인 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로를 설계하였다. 공급전원이 낮아지더라도 외부 프로그램 전원을 사용하여 높은 프로그램 파워를 eFuse (electrical fuse)에 공급하면서 셀의 읽기 전류를 줄일 수 있는 듀얼 포트 eFuse 셀을 제안하였다. 그리고 제안된 듀얼 포트 eFuse 셀은 파워-온 읽기 기능으로 eFuse의 프로그램 정보가 D-래치에 자동적으로 저장되도록 설계하였다. 또한 메모리 리페어 주소와 메모리 액세스 주소를 비교하는 주소 비교 회로는 dynamic pseudo NMOS 로직으로 구현하여 기존의 CMOS 로직을 이용한 경우 보다 레이아웃 면적을 19% 정도 줄였다. 전기적인 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로는 동부하이텍 <TEX>$0.11{\mu}m$</TEX> Mixed Signal 공정을 이용하여 설계되었으며, 레이아웃 면적은 <TEX>$249.02{\times}225.04{\mu}m^{2}$</TEX>이다. In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's <TEX>$0.11{\mu}m$</TEX> mixed signal process is <TEX>$249.02 {\times}225.04{\mu}m^{2}$</TEX>.

Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double-gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness comparisons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60-70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node.

Ultra-low-power DLMS adaptive filter for hearing aid applications

We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 /spl mu/m, 23.1 kHz, 21.4 nW, 8/spl times/8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.

CMOS LOGIC FAMILIES FOR VLSI DESIGN

In this paper, the investigation and evaluation of different stateof-the-art CMOS logic families, currently in use for VLSI design, are performed. These logic families are static CMOS logic, Pseudo-NMOS logic, Domino logic and Two-phase dynamic logic (TPDL). The main characteristics of these logic families, which are, power consumption, layout area and ease of implementation, are analyzed and compared. For the comparison among the different logic families, three basic logic gates are implemented using each of these logic families. The implemented gates are an Inverter, a 2-input NAND, and a 2-input NOR gates. The simulation is performed icing Tanner-Pro tools for different technologies starting from 1.6 urn to 0.25 um feature size at a power supply voltage (Vdd) of 5 volts. The technology parameters were extracted and measured from a fabrication lot by MOSIS SCN16 to SCNO25.

Modeling and testing for stuck faults in pseudo nMOS combinational circuits

In this paper, a new transistor model is developed. This model employs the logic transistor function (LTF) to examine the behavior of pseudo nMOS logic circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the following logic values (0, 1, I, M). I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults are analyzed in the model. An algorithm that is based on a modified version of the Boolean difference technique is applied to obtain test vectors. Primitive D-cubes of the fault are extracted for a specified sub circuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used.

A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 mu m CMOS

Using a combination of architecture optimization techniques and unconventional circuit designs, a 60 MHz decision-feedback equalizer (DFE) chip is presented for high-bit-rate digital modem applications. The equalizer can accommodate quaternary phase-shift keying (QPSK), and 16, 64, and 256 quadrature amplitude modulation (QAM) and achieves a peak throughput rate of 480 MB/s. The chip contains four complex-valued programmable filter taps and incorporates coefficient updating circuitry for implementing the LMS adaptive algorithm with user-selectable adaptation step sizes. Cut-set retiming architecture techniques were used so that the chips could be cascaded to implement longer equalizer lengths without any speed degradation, and a circuit design technique called adaptively biased pseudo-NMOS logic (APNL) was adopted to reduce on-chip critical-path delays. The fully parallel chip architecture achieves a computational throughput of 1.44 billion operations per second (GOPS).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>