WITHDRAWN: Parametric analysis of schematic for efficient sub-system design with MOSFET’s scaling factors

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Abstract Integrated Circuits (IC) focus on low power devices, as per the demand in industries. In VLSI circuits, for modern applications, power dissipation is an essential constraint as it plays a crucial role in the system’s overall performance estimation. Many techniques, like power gating or clock gating, can be used to reduce unnecessary power consumption. Non-working parts would be switched off during the non-functional period. IC designers are still facing the problem of choosing the best logic among different styles for the set of user-defined constraints. It is easy to select the optimal, with the prior availability of metrics, to make the design efficient. In this paper, the analysis was done on Mentor Graphics EDA Tool with 130nm technology to predict the characterization of given logic with multiple scaling factors and tested through distinct voltages by continuously changing MOSFET dimensions. The clocked CMOS is like CMOS in some conditions at the cost of power dissipation (196.49uW in CCMOS and 100.24nW in CMOS). Pseudo nMOS is suffering from delay variations (with 117.97pS to 503.74 pS) by changing MOS size and input voltage in their characteristics, unlike CMOS logic. It is to notice that the CMOS and clocked CMOS logics are ideal in maintaining constant delays in response to change in FET dimensions or supply voltages. Similarly, pseudo-NMOS logic, otherwise, is a delightful choice to use (with an average power maximum of 108.54 nW) when a constant power dissipation is mandatory from the system even, it’s far operated in vibrant conditions. Identified efficient schematic which is either essential to arrive the most effective sub-system, which in turn increases the overall system performance.