Design and Analysis of Conventional and Ratioed Cmos Logic Circuit

Abstract

This paper compares the ratioed logic circuits and conventional CMOS design. This comparison performed on efficient CMOS circuit realizations and the ratioed logic circuits and it is resulted in to superiority of ratioed circuit over the conventional CMOS in some cases with respect to area, input capacitance. In this paper, 4-input NAND gate is designed using the conventional CMOS design and pseudoNMOS logic design, which is the most common form of CMOS ratioed logic and the results are compared using Microwind and DSCH2 CMOS layout tools.