Ps Rms Jitter Research Articles

Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter

SUMMARY This paper demonstrates a pulse width controlled PLL without using an LPF. A pulse width controlled oscillator accepts the PFD output where its pulse width controls the oscillation frequency. In the pulse width controlled oscillator, the input pulse width is converted into soft thermometer code through a time to soft thermometer code converter and the code controls the ring oscillator frequency. By using this scheme, our PLL realizes LPF-less as well as quantization noise free operation. The prototype chip achieves 60 μm × 20 μm layout area using 65 nm CMOS technology along with 1.73 ps rms jitter while consuming 2.81 mW under a 1.2 V supply with 3.125 GHz output frequency.

A SEAMLESS-CONTROLLED DIGITAL PLL USING DUAL LOOPS FOR HIGH SPEED SOCS

A new dual-loop digital phased-locked loop (DPLL) architecture is presented. This novel architecture is designed to provide a wide operating frequency range, high precision, and small jitter, and fits over a relatively small area. To achieve these characteristics, the architecture is implemented using a coarse loop with an UP/DOWN counter and a coarse digital-to-analog converter (DAC) to rapidly reduce the phase error, and a fine loop with a time-to-digital converter (TDC) and a fine DAC to provide more precision. Furthermore, the seamless-frequency tracking architecture based on a code conversion between the coarse cell and the fine cell of the DAC is devised to improve the lock-in stability. The chip is fabricated with Dongbu HiTek 0.18-μm CMOS technology. It has a wide operation range of 0.4–1.4 GHz, and an area of 0.195 mm2. The measured results show 15.64 ps peak-to-peak jitter and 2.22 ps rms jitter, and a power dissipation of 16.2 mW at 1 GHz.

A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor

A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS

A new topology in PLL architecture dual-mode KVCO (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65 nm CMOS and shows about 3 ps RMS jitter, phase noise of −107 and −109 dBc/Hz at 100 kHz, 1 MHz offset frequency and reference spur of 68.5 dBc.

Low-noise wideband PLL with dual-mode ring-VCO

A low-jitter 110 MHz-to-620 MHz phase-locked loop (PLL) that includes a low-noise wide-frequency-range ring oscillator with a dual-mode operation is presented. The measurement results using a 65 nm low-power CMOS process show that the proposed PLL achieves as low as a 2.5 ps RMS jitter at 600 MHz of output frequency while consuming 2.7 mW at a 1.2 V supply. The die area is only 0.09 mm2.

A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation

A new technique utilizing two-point (TP) modulation for a spread spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a digital SigmaDelta modulator, and the voltage-controlled oscillator is modulated analogically. With this technique, the modulation bandwidth is enhanced in order that the modulation profile accuracy and jitter performance caused by the SigmaDelta modulator can be improved at the same time. The order of the SigmaDelta modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies specifications. The dual-path loop filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18 mum CMOS process. The size of the chip area is 0.44 times 0.48 mm2. The circuit produces a clock of 1.5 GHz with a down-modulation ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter, and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.

A CMOS UWB Pulse Generator for 6&amp;#x2013;10 GHz Applications

A CMOS ultra wideband (UWB) pulse generator with low energy dissipation and high peak amplitude is presented for 6-10 GHz applications. The pulse generator complies with the FCC spectral mask for indoor UWB systems. It consists of a glitch generator, a pulsed oscillator, and a pulse shaping filter. The pulsed oscillator is switched on by the glitch signal only for a short duration, so as to make a UWB pulse. For sub-nanosecond pulse generation, a pulsed oscillator with fast transient response is proposed. A pulse shaping filter makes the oscillator output fall into the FCC spectral mask. The pulse generator is fabricated using a 0.18 mum CMOS process. The core chip has a size of 0.11 mm2. It shows pulse duration of about 500 ps with -10 dB bandwidth of 4.5 GHz from 5.9 to 10.4 GHz. The energy consumption is 27.6 pJ per pulse with a peak-to-peak amplitude of 673 mV on a 50 Omega output load. The generated pulses are very coherent with 1.8 ps RMS jitter.

A 0.4 ps-RMS-Jitter 1–3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents the design and experimental results of a 0.4 ps rms jitter (integrated from 3 kHz to 300 MHz offset at 2.5 GHz) 1–3 GHz tunable ring-oscillator PLL for integrated clock multiplier applications. A new loop filter structure based on a sample-reset phase-to-voltage converter and a <emphasis emphasistype="boldital">Gm-C</emphasis> filter decouples reference spur performance from charge-pump current matching and loop filter leakage, while enables phase error preamplification to lower PLL in-band noise without reducing VCO analog tuning range or increasing loop filter capacitor size. The ring-oscillator VCO features programmability of phase noise and power consumption at a given frequency. The PLL is implemented in a digital 0.13 <formula formulatype="inline"><tex Notation="TeX">$\mu{\hbox{m}}$</tex></formula> CMOS process using only 1.2 V devices, occupies 0.07 <formula formulatype="inline"><tex Notation="TeX">${\hbox{mm}}^{2}$</tex> </formula> and consumes 23 mW excluding reference clock receiver for 2.5 GHz output at the lowest phase noise mode. </para>

A DLL-Based Programmable Clock Multiplier in 0.18-$\mu$m CMOS With ${-}$70 dBc Reference Spur

This paper describes a 150-400 MHz programmable clock multiplier which uses a recirculating DLL. The clock multiplier uses a sampling phase detector and employs chopping, autozeroing and various other circuit techniques to reduce static phase offset and crosstalk between the reference and the output clock. The DLL is implemented in 0.18-mum CMOS, consumes 16 mW of power, and achieves 1-5 ps RMS jitter and -70 dBc reference spur level.

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm2

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance

Integrated optical payload envelope detection and label recovery device for optical packet switching networks

We demonstrate an integrated device for optical payload envelope detection and optical label recovery for optical packet switching. The device is designed to handle asynchronous serially labeled packets with variable length 40 Gbps payloads preceded by 10 Gbps labels. The device outputs two signals: 1. a payload envelope signal corresponding to the temporal location and duration of the optical payload and 2. an electrical label recovered from the optical label. The payload envelope signal has rise and fall times of 3 ns with 150 ps RMS jitter and is used to perform error free label erasure and rewriting. Error free label recovery is also demonstrated.

A behavioral modeling approach to the design of a low jitter clock source

Designing a low-jitter clock synthesizer is not a trivial task. Multiple noise and disturbance sources combine together in the nonlinear blocks of the phased-lock loop (PLL) affecting its performance. Moreover, deceptively small circuit nonideal characteristics can have nonnegligible effects in the behavior of the whole system. A behavioral modeling approach allowing a systematic design of the PLL is discussed here. This approach allows the designer to maintain a grasp of the fundamentals using coarse models at the early stage of the design and to eventually gain insight on the lower order effects by gradually increasing the level of detail as the design develops. Moreover, accurate design specifications for the actual circuit blocks are obtained and, eventually the transistor-level results can be back-annotated into the behavioral model for further verification. This methodology is here demonstrated in the context of the modeling, design and the implementation of a fully integrated BiCMOS 1.76 ps rms jitter 180-MHz clock synthesizer. A detailed functional model including the crystal oscillator, the main circuit nonlinearities, and noise sources of the PLL is presented. The building blocks' models development has been motivated by actual circuit implementations. Moreover, computational pitfalls have been identified and solutions have been proposed. Finally, the key behavioral model results have been compared against measured results obtained from an actual fabricated prototype validating the effectiveness of the proposed approach.

A monolithic gallium arsenide interval timer IC with integrated PLL clock synthesis having 500-ps single shot resolution

A gallium arsenide (GaAs) integrated circuit for measuring single shot time intervals with 500-ps resolution has been designed, fabricated, and tested. The circuit contains a 12-b counter that can be extended externally and control circuitry for the detection of multiple intervals. Options such as number of intervals, minimum interval time, and timing resolution are user programmable. The circuit employs a self-contained 2.0-GHz phase-locked loop (PLL) clock synthesizer with less than 5 ps rms jitter and a lock time of 2.5 /spl mu/s. The circuit is packaged in a 14-mm/sup 2/, 52-pin thermally enhanced plastic package and operates from a single +5-V supply. The nominal power dissipation is 2.8 W. The circuit is fabricated in a 0.6-/spl mu/m gate length, enhancement/depletion GaAs MESFET process utilizing four layers of gold interconnect metallization. Inductors, capacitors, and thin film resistors can be fabricated in this process, enabling integrated analog circuitry. The die size is 3.28 by 3.15 mm. The circuit has applications in collision avoidance sensors, laser rangefinders, surveying, police radar, and test instrumentation.