Abstract
A new dual-loop digital phased-locked loop (DPLL) architecture is presented. This novel architecture is designed to provide a wide operating frequency range, high precision, and small jitter, and fits over a relatively small area. To achieve these characteristics, the architecture is implemented using a coarse loop with an UP/DOWN counter and a coarse digital-to-analog converter (DAC) to rapidly reduce the phase error, and a fine loop with a time-to-digital converter (TDC) and a fine DAC to provide more precision. Furthermore, the seamless-frequency tracking architecture based on a code conversion between the coarse cell and the fine cell of the DAC is devised to improve the lock-in stability. The chip is fabricated with Dongbu HiTek 0.18-μm CMOS technology. It has a wide operation range of 0.4–1.4 GHz, and an area of 0.195 mm2. The measured results show 15.64 ps peak-to-peak jitter and 2.22 ps rms jitter, and a power dissipation of 16.2 mW at 1 GHz.
Published Version
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