Prototype Chip Research Articles

A VHF insect-tracking radio-telemeter ASIC with on-chip power-regulation in 65-nm CMOS

This paper demonstrates a VHF radio-telemeter ASIC which for the first time can replace the PCB based telemeter circuit to yield around 37 % miniaturization in size and weight of the state-of-the-art in insect-telemeter and facilitate wireless-tracking of small flying insects in real-time. The chip employs the newly developed all-digital method of ultra-low duty-cycle generation technique, which unlike all the previous techniques does not require any passive components. The ASIC is designed to generate FSK modulated 8-bit coded burst-mode radio-signal at 0.0078 duty-cycle with a signal-window width of 13.1 ms using an on-chip oscillator operating at around 160 MHz. The oscillator frequency was temperature compensated employing a CTAT voltage-supply from a Power-Regulation Unit (PRU) integrated on the ASIC. The PRU steps down the 1.55V supply-voltage for the operation of the ASIC telemeter and consists of CTAT and Band-gap voltage-reference circuits along-with two voltage-regulators, one to drive the digital core-circuitry with temperature compensation and the other to supply the output-driver at constant 1V. The prototype chip was fabricated on a 1mm × 1 mm chip in TSMC 65nmGP CMOS process and the functional performance was experimentally verified against supply-voltage and temperature variation.

Design and evaluation of UKRI-MPW0: a monolithic HV-CMOS pixel sensor with backside biasing

High-Voltage CMOS (HV-CMOS) pixel sensor technology is the most promising route for achieving thin, monolithic pixel detectors with excellent radiation tolerance, as required by future tracking applications in physics experiments, such as the High Luminosity LHC. This paper introduces a U.K. Research and Innovation funded Multi-Project Wafer prototype chip UKRI-MPW0, which is an HV-CMOS pixel sensor designed to push the performance parameters of these detectors. Having a novel sensor cross-section optimised for backside biasing to unprecedented high voltages, UKRI-MPW0 demonstrates the capability to withstand bias voltages of up to 600 V, surpassing the current state-of-the-art and promising enhanced radiation tolerance. The paper provides a detailed description of the design and performance evaluation results of UKRI-MPW0.

Mixed‐mode SNN crossbar array with embedded dummy switch and mid‐node pre‐charge scheme

AbstractThis paper presents a membrane computation error‐minimized mixed‐mode spiking neural network (SNN) crossbar array. Our approach involves implementing an embedded dummy switch scheme and a mid‐node pre‐charge scheme to construct a high‐precision current‐mode synapse. We effectively suppressed charge sharing between membrane capacitors and the parasitic capacitance of synapses that results in membrane computation error. A 400 × 20 SNN crossbar prototype chip is fabricated via a 28‐nm FDSOI CMOS process, and 20 MNIST patterns with their sizes reduced to 20 × 20 pixels are successfully recognized under 411 μW of power consumed. Moreover, the peak‐to‐peak deviation of the normalized output spike count measured from the 21 fabricated SNN prototype chips is within 16.5% from the ideal value, including sample‐wise random variations.

First results on the final readout chip for the High-Luminosity LHC upgrade of the CMS Inner Tracker

The CMS Readout Chip (CROC) is a 65nm CMOS hybrid pixel readout chip for the High-Luminosity LHC upgrade of the CMS Inner Tracker. The chip has been developed by the CERN RD53 Collaboration in order to withstand radiation doses up to 10MGy and hit rates up to 3GHzcm−2 on the innermost tracking layer. Moreover, it must handle an increased sensor granularity (pixel size of 2500µm2) with respect to current detectors and operate at detection thresholds as low as 1000e. Twenty wafers of the prototype chip (CROCv1) have been produced in 2021. The CROCv1 characterisation and verification campaign has, overall, demonstrated the radiation resistance of the chip and its performance. The production version of the chip (CROCv2) was submitted in October 2023 and the engineering run wafers have been received in January 2024. In this contribution, the first results from CROCv2 wafer-level testing of more than 1900 chips from the engineering run will be outlined.

Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements

Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements

A Power-Efficient Envelope-Detector-Less Amplitude-Shift-Keying Forward Telemetry for Wirelessly Powered Biomedical Devices.

This paper proposes an envelope-detector-less (EDL) amplitude-shift-keying (ASK) forward telemetry (FT) demodulator for wireless power/data transfer (WPDT) systems. The EDL ASK FT demodulator can substitute bulky and power-hungry components, which are an envelope detector and an analog comparator in the conventional ASK FT demodulator, with a digital controller, reducing both power dissipation and chip area. The proposed demodulator shares the gate control signals of pass transistors, which are used in an ac-dc regulator for wireless power reception, to maintain a constant load voltage while efficiently demodulating the forward telemetry data. Also, a proposed digital cleaner in the EDL demodulator refines this control signal into a wide pulse without suffering from resonant frequency noise, while a synchronizer can align its frequency with the data rate and resonant frequency. The 0.25-μm CMOS prototype chip of the proposed power-path-less EDL ASK FT demodulator, equipped with the ac-dc regulator, demonstrates a significant 38.2% reduction in power dissipation compared to the conventional ASK FT demodulator. Moreover, the EDL ASK FT demodulator occupies only 0.023-mm2 silicon area and achieves a low bit error rate (BER) less than 10-4 while maintaining a regulated voltage of 4.5 V on the load.

An 11-bit SAR ADC for high frame rate and high-dynamic X-ray imaging at future XFELs

The paper presents the design and test results of an 11-bit successive approximation register (SAR) ADC, suitable for massive on-chip integration in a pixel readout chip. The objective is to establish new digital readout architectures for X-ray pixel detectors at future X-ray free electron laser (XFEL) facilities, enabling high frame rates and a high dynamic range simultaneously. The prototype chip has been designed and fabricated in a 130 nm CMOS process, with the core circuit occupying an area of ~ 0.034 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.78/-0.78 LSB and +0.58/-0.52 LSB, respectively. The signal-to-noise-and-distortion ratio (SINAD) is 61.6 dB at 2 MS/s, achieving an effective number of bit (ENOB) of ~ 9.94-bit. The core circuit power consumption is 47 μW at 2 MS/s with a 1.2 V supply.

An NMOS output-capacitorless low-dropout regulator with dynamic-strength event-driven charge pump

In this paper, an NMOS output-capacitorless low-dropout regulator (OCL-LDO) featuring dual-loop regulation has been proposed, achieving fast transient response with low power consumption. An event-driven charge pump (CP) loop with the dynamic strength control (DSC), is proposed in this paper, which overcomes trade-offs inherent in conventional structures. The presented design addresses and resolves the large signal stability issue, which has been previously overlooked in the event-driven charge pump structure. This breakthrough allows for the full exploitation of the charge-pump structure's potential, particularly in enhancing transient recovery. Moreover, a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage, leading to favorable static characteristics. A prototype chip has been fabricated in 65 nm CMOS technology. The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current (I Q) and can recover within 30 ns under 200 mA/10 ns loading change.

A Hybrid Scheme for TX I/Q Imbalance Self-Calibration in a Direct-Conversion Transceiver

A generic transmitter (TX) I/Q imbalance self-calibration method, which was designed based on a hybrid analog and digital structure, is proposed in this paper. The whole calibration scheme was implemented using low-complexity digital–analog circuits based on a zero-force feedback loop. In order to eliminate the negative effect of local oscillator (LO) harmonics on the calibration, we used a variable-delay line (VDL) in the analog domain instead of the digital phase compensator. The prototype chip was fabricated within a 0.2∼5.0 GHz direct-conversion transmitter in a 65 nm CMOS process, and measurements found an image rejection ratio (IRR) of 65 dBc.

Sensitivity studies and optimization of an impedance-based biosensor for point-of-care applications

In this study, we examined the relationship between the sensitivity of interdigitated electrode (IDE) impedimetric biosensors and the gap between the IDEs. Our aim is to find an optimal design to maximize sensitivity. A three-dimensional COMSOL model was constructed for determining the effects of electrode gap, width, and height on impedance sensitivity, revealing a singular linear correlation with the inner gap. Considering both the simulation results and fabrication processes, we have developed three IDE prototype chips with electrode gaps of 3 μm, 4 μm, and 5 μm, respectively. For empirical validation, human anti-SARS-CoV-2 monoclonal antibody (mAb) was utilized, with immobilization of the SARS-CoV-2 spike protein on the chip's surface for mAb capture. This interaction, further amplified by Protein G conjugation, induced shifts in the impedance spectrum. The sensitivity of each prototype chip was evaluated across mAb concentrations ranging from 50 ng/mL to 500 ng/mL. The 3 μm configuration emerged as the most sensitive, demonstrating the ability to detect mAb concentrations as low as 50 ng/mL, a threshold unattainable by the other designs. This outcome underscores the critical influence of reduced inter-electrode gap on enhancing biosensor detection limits. The findings from this investigation offer a foundational approach for advancing biosensor sensitivity via electrode geometric optimization, with broad potential applications extending beyond COVID-19 diagnostics to a wide spectrum of clinical and research contexts.

NAPA-p1: monolithic nanosecond timing pixel for large area sensors, designed for future e + e - colliders

NAPA-p1 is a prototype Monolithic Active Pixel Sensor 'MAPS' developed as a first iteration towards meeting the detectors general requirements for future e + e - colliders. Long-term objective is to develop a wafer-scale sensor in MAPS with an area ∼ 10 cm × 10 cm. This article presents the motivations for the design choices of NAPA-p1, translating the physics requirement into circuit specifications. Simulations show a pixel jitter of < 400 ps-rms and an equivalent noise charge of 13 e -rms with an average power consumption of 1.15 mW/cm2 assuming a 1% duty cycle, meeting the target specifications. The prototype is designed in 65 nm CMOS imaging technology, with dimensions of 1.5 mm × 1.5 mm and a pixel pitch of 25 μm. The prototype chip has been fabricated and characterization results will be available soon.

Integration of EDWARD readout architecture in full-field fluorescence imaging detector

Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are a constant challenge. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD (Event-Driven With Access and Reset Decoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one, named 3FI65P1, is a full device with the analog pixel circuitry suited for full-field fluorescence imaging. It is already manufactured, and preliminary results are presented. The second chip, named EDWARD65P1, contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of the EDWARD architecture alone.

Optimized design and characterization of HYLITE, a charge-integration readout chip of XFEL

HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel readout chip designed for SHINE (Shanghai HIgh repetition rate XFEL aNd Extreme light facility). The target specifications for the full-size HYLITE chip include a pixel matrix of 128 × 128 pixels and a frame rate of 10 kHz. In order to meet these specifications, two small-scale chips, designated HYLITE0.1 and HYLITE0.2, were fabricated and underwent comprehensive testing. Some issues were discovered during tests including the noise performance and the error of output ADU (Analog Digital Units) codes.The HYLITE200S represents the third prototype chip developed to address the above issues. The CDS (Correlated Double Sampling) circuits and glitch-clear clock structures are integrated in pixels. Furthermore, to meet the data output rate requirements of the full-size chip, a high-speed data interface has been designed. Test results show that the signal-to-noise ratio is improved to 9.31 for a 12 keV single photon, and the ADU error is fixed. By integrating a phase-locked loop and a balanced encoding logic, the data interface can work steadily at a speed of 3.125 Gbps.

WASA: a low power and high integration readout ASIC for TPCs in 65 nm CMOS

The paper presents the development of a low-power and high-integration readout ASIC (WASA) for time projection chambers (TPCs). Each channel of the ASIC consists of the analog front-end, a waveform sampling ADC and digital signal processing circuits. To reduce power consumption, a simple CR-RC shaper and a digital trapezoid filter are adopted to achieve comparable performance to a CR-RC4 shaper with much lower power. Trigger logic and data buffer have also been integrated to reduce the data bandwidth. A 16-channel prototype chip was fabricated in a 65 nm CMOS process and was tested. The test results were consistent with the simulation. At 40 MSPS sampling rate, the power consumption of the chip was only 4.94 mW per channel, including 1.38 mW from the analog front-end, 0.83 mW from the waveform sampling ADC and 2.73 mW from digital logics. The equivalent noise charge of 569 e+14.8 e/pF has been achieved. The measured dynamic range was 120 fC and the integral nonlinearity was less than 0.74%. More design details and test results will be given in this paper.

Achieving High-Precision, Low-Cost Microfluidic Chip Fabrication with Flexible PCB Technology.

Soft lithography has long remained the state of the art to generate the necessary micropatterning for molded microfluidic (MF) chips. Previous attempts to use printed circuit boards (PCBs) as a cheap and accessible alternative to expensive lithographed molds for the production of PDMS MF chip prototypes have shown their limitations. A more in-depth exploration of using PCBs as a mold substrate and a novel methodology of using flexible PCBs to produce highly accurate MF chips is reported here for the first time. Cross sections highlight the improved accuracy of this method, and peel testing is performed to demonstrate suitable adhesion between the glass substrate and PDMS cast. Positive cell growth viability showcases this novel method as a high-accuracy, high-accessibility, low-cost prototyping method for microfluidic chips while still maintaining all favorable properties provided by the PDMS material.

Sub-50 mV power supply, recursive stacking body bias NAND gate for extremely low-voltage CMOS LSIs

This paper presents a recursive stacking body-bias NAND for extremely low voltage application. Our proposed NAND utilizes recursive-stacking and body-bias techniques to achieve extremely low-voltage operation. The former suppresses off-leakage current of MOSFETs and enhances the voltage gain of the NAND gate. The latter achieves on-current enhancement and the voltage gain improvement of the NAND gate. Performance improvements of our proposed NAND gate are theoretically analyzed and discussed. Simulation of our proposed NAND gates showed that voltage transfer curves, voltage gains, and voltage swings were improved significantly. A prototype chip was fabricated in a 180 nm CMOS process and demonstrated that the voltage swing of the proposed NAND was 44.1 mV at 50 mV power supply, which was 16.4 mV improvement compared to that of the standard NAND gate, at the cost of area, power, and delay time.

Development of the Continuous Readout Digitising Imager Array detector

The CoRDIA project aims to develop an X-ray imager capable of continuous operation in excess of 100 kframe/s. The goal is to provide a suitable instrument for Photon Science experiments at diffraction-limited Synchrotron Rings and Free Electron Lasers considering Continuous Wave operation. Several chip prototypes were designed in a 65 nm process: in this paper we will present an overview of the challenges and solutions adopted in the ASIC design.

Measurement Approach to Evaluation of Ultra-Low-Voltage Amplifier ASICs

Abstract This article presents measurement circuits and a test board developed for the experimental evaluation of prototype chip samples of the Fully Differential Difference Amplifier (FDDA). The Device Under Test (DUT) is an ultra low-voltage, high performance integrated FDDA designed and fabricated in 130nm CMOS technology. The power supply voltage of the FDDA is 400mV. The measurement circuits were implemented on the test board with the fabricated FDDA chip to evaluate its main parameters and properties. In this work, we focus on evaluation of the following parameters: the input offset voltage, the common-mode rejection ratio, and the power supply rejection ratio. The test board was developed and verified. The test board error was measured to be 38.73mV. The offset voltage of the FDDA was −0.66mV. The measured FDDA gain and gain bandwidth were 48dB and 550kHz, respectively. In addition to the measurement board, a graphical user interface was also developed to simplify the control of the device under test during measurements.

A Voltage-Assist 16-Channel Electrochemical Biosensor with Linearity Compensation.

Large capacitive loading of electrodes induces massive error current and imperfect settling in the electrochemical signal acquisition process, leading to inaccurate acquisition results. To efficiently mitigate this inaccuracy, this paper presents a current-and-voltage dual-mode acquisition technique in which a voltage front-end (VFE) is employed to acquire the electrode voltage error and compensate the nonlinearity induced by the electrode capacitive loading. Therefore, the gain and bandwidth requirements of the current front end (CFE) can be relaxed to reduce the complexity and power consumption. With a relieved gain requirement, an inverter-based capacitive trans-impedance amplifier (IB-CTIA) is adopted to boost the input transconductance for low-noise design. By reusing the supply current, the IB-CTIA effectively achieves a low input-referred current noise of 3.9 pArms and a dynamic range (DR) of 126 dB with only 18-μW static power. The prototype chip is fabricated in a 180-nm CMOS process. Interleukin-6 immunoassays (IL-6) are implemented to verify the chip's performance. With the proposed nonlinear error compensation, the correlation coefficient of the detection result is improved from 0.951 to 0.980 and the limit of detection (LoD) is reduced from 8.31 pg/mL to 6.90 pg/mL.

MorphBungee: A 65-nm 7.2-mm2 27-μJ/image Digital Edge Neuromorphic Chip with On-Chip 802-frame/s Multi-Layer Spiking Neural Network Learning.

This paper presents a digital edge neuromorphic spiking neural network (SNN) processor chip for a variety of edge intelligent cognitive applications. This processor allows high-speed, high-accuracy and fully on-chip spike-timing-based multi-layer SNN learning. It is characteristic of hierarchical multi-core architecture, event-driven processing paradigm, meta-crossbar for efficient spike communication, and hybrid and reconfigurable parallelism. A prototype chip occupying an active silicon area of 7.2 mm2 was fabricated using a 65-nm 1P9M CMOS process. when running a 256-256-256-256-200 4-layer fully-connected SNN on downscaled 16 × 16 MNIST images. it typically achieved a high-speed throughput of 802 and 2270 frames/s for on-chip learning and inference, respectively, with a relatively low power dissipation of around 61 mW at a 100 MHz clock rate under a 1.0V core power supply, Our on-chip learning results in comparably high visual recognition accuracies of 96.06%, 83.38%, 84.53%, 99.22% and 100% on the MNIST, Fashion-MNIST, ETH-80, Yale-10 and ORL-10 datasets, respectively. In addition, we have successfully applied our neuromorphic chip to demonstrate high-resolution satellite cloud image segmentation and non-visual tasks including olfactory classification and textural news categorization. These results indicate that our neuromorphic chip is suitable for various intelligent edge systems under restricted cost, energy and latency budgets while requiring in-situ self-adaptative learning capability.