Prototype ASIC Research Articles

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD endcap timing layer (ETL) upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors to detect charged particles, with the goal to achieve a time resolution of 40–50 ps per hit, and 30–40 ps per track with hits from two detector layers. The ETROC1 is composed of a 5 × 5 pixel array and peripheral circuits. The pixel array includes a 4 × 4 active pixel array with an H-tree shaped network delivering clock and charge injection signals. Each active pixel is composed of various components, including a bump pad, a charge injection circuit, a pre-amplifier, a discriminator, a digital-to-analog converter, and a time-to-digital converter. These components play essential roles as the front-end link in processing LGAD signals and measuring timing-related information. The peripheral circuits provide clock signals and readout functionalities. The size of the ETROC1 chip is 7 mm× 9 mm. ETROC1 has been fabricated in a 65 nm CMOS process, and extensively tested under stimuli of charge injection, infrared laser, and proton beam. The time resolution of bump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in the beam test.

Testbeam results of irradiated SiGe BiCMOS monolithic silicon pixel detector without internal gain layer

Samples of the monolithic silicon pixel ASIC prototype produced in 2022 within the framework of the Horizon 2020 MONOLITH ERC Advanced project were irradiated with 70 MeV protons up to a fluence of 1 × 1016 neq/cm2, and then tested using a beam of 120 GeV/c pions. The ASIC contains a matrix of 100 μm pitch hexagonal pixels, read out by low noise and very fast frontend electronics produced in a 130 nm SiGe BiCMOS technology process. The dependence on the proton fluence of the efficiency and the time resolution of this prototype was measured with the frontend electronics operated at a power density between 0.13 and 0.9 W/cm2. The testbeam data show that the detection efficiency of 99.96% measured at sensor bias voltage of 200 V before irradiation becomes 96.2% after a fluence of 1 × 1016 neq/cm2. An increase of the sensor bias voltage to 300 V provides an efficiency to 99.7% at that proton fluence. The timing resolution of 20 ps measured before irradiation rises for a proton fluence of 1 × 1016 neq/cm2 to 53 and 45 ps at HV = 200 and 300 V, respectively.

Development of the Beam Conditions Monitoring Prime system for beam abort and luminosity monitoring in ATLAS based on a segmented polycrystalline CVD diamond system and dedicated front-end ASIC

The High Luminosity upgrade of Large Hadron Collider (HL-LHC) will increase the LHC luminosity and with it the density of particles on the detector by an order of magnitude. For protecting the inner silicon detectors of the ATLAS experiment and for monitoring the delivered luminosity, a radiation hard beam monitor was developed based on polycrystalline Chemical Vapor Deposition (pCVD) diamond detectors and a new dedicated rad-hard front-end ASIC. Due to the large range of particle flux through the detector, flexibility is very important. To satisfy the requirements imposed by the HL-LHC, our solution is based on segmenting diamond sensors into devices of varying size and reading them out with new multichannel readout ASICs divided into two independent parts — each of them serving one of the tasks of the system. This paper describes the system design including detectors, electronics, mechanics and services and presents preliminary results from the most recent detectors fabricated, using our prototype ASIC with data from beam tests at CERN.

Ultra-Fast Energy Resolved Imager for `Pseudo' Laue diffraction experiments at synchrotron facilities

`Pseudo' Laue diffraction experiments, with multi pink beam, is being considered as an option for the upgrade of SOLEIL for fast time resolved crystallographic applications in the energy range from 5 to 30 keV. An important requirement for the detector of such experiments is to increase the readout speed and the capability to discriminate between several energies.For this purpose, a new project has been launched in 2021 through a collaboration between SOLEIL and AGH, starting with a feasibility phase with the design and realization of a new photon counting ASIC prototype, named UFERI (Ultra-Fast Energy Resolved Imager). After a short description of the ASIC requirements and main architecture, first results of the ASIC prototypes are presented, as well as preliminary results of the first hybrid pixel modules illuminated with X-rays in our laboratory.

Edims: an event-driven internal memory synchronized readout prototype ASIC chip developed for HFRS-TPC

Edims: an event-driven internal memory synchronized readout prototype ASIC chip developed for HFRS-TPC

An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs

The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC, developed for multi-channel readout systems, in particular for applications in particle physics experiments, are discussed. A prototype ASIC was designed and fabricated in 130 nm CMOS technology and a wide spectrum of static (INL<0.4 LSB, DNL<0.3 LSB) and dynamic (ENOB=9.45) measurements was performed to study and quantify the performance of ADC.The ADC converts analogue signals with a sampling frequency up to 55 MHz and power consumption below 1 mW.The ADC works asynchronously, so no external clock is required. The ADC Figure of Merit (FOM) at 50 MHz sampling frequency is 24 fJ/conv.-step, and is the lowest among the State of the Art designs with similar technology and specifications.

Recording channel design for time-based measurements in 28 nm CMOS

In this paper we present a recording stage dedicated to time-based measurements required in imaging detectors. The prototype ASIC is manufactured in the 28 nm CMOS process and consists of a 8 × 4-pixel matrix of 50 μm pitch. Each pixel includes a recording stage that processes input signals for the digital circuitry, responsible for performing time-based measurements such as Time-over-Threshold and Time-of-Arrival. The digital part of the pixel is made up of two ring-based oscillators, configuration registers, and counters. The recording channel occupies only 12 × 50 μm while consuming 4.5 μA current. The in-pixel coarse and fine correction methods implemented allowed an improvement of gain and offset uniformity 3.3 and 10 times, respectively.

Performance of a front-end prototype ASIC for the ATLAS High Granularity timing detector

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a 5 × 5-pad matrix and contains the analog part of the single-channel readout (preamplifier, discriminator, two TDCs and SRAM). Two preamplifier architectures (transimpedance and voltage) were implemented and tested. The ASIC was characterised both alone and as a module when connected to a 5 × 5-pad array of LGAD sensors. In calibration measurements, the ASIC operating alone was found to satisfy the technical requirements for the project, with similar performances for both preamplifier types. In particular, the jitter was found to be 15 ± 1 ps (35 ± 1 ps) for an injected charge of 10 fC (4 fC). A degradation in performance was observed when the ASIC was connected to the LGAD array. This is attributed to digital couplings at the entrance of the preamplifiers. When the ASIC is connected to the LGAD array, the lowest detectable charge increased from 1.5 fC to 3.4 fC. As a consequence, the jitter increased for an injected charge of 4 fC. Despite this increase, ALTIROC1 still satisfies the maximum jitter specification (below 65 ps) for the HGTD project. This coupling issue also affects the time over threshold measurements and the time-walk correction can only be performed with transimpedance preamplifiers. Beam test measurements with a pion beam at CERN were also undertaken to evaluate the performance of the module. The best time resolution obtained using only ALTIROC TDC data was 46.3 ± 0.7 ps for a restricted time of arrival range where the coupling issue is minimized. The residual time-walk contribution is equal to 23 ps and is the dominant electronic noise contribution to the time resolution at 15 fC.

Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration

Owning a high-end semiconductor foundry is a luxury very few companies can afford. Thus, fabless design companies outsource integrated circuit fabrication to third parties. Within foundries, rogue elements may gain access to the customer’s layout and perform malicious acts, including the insertion of a hardware trojan (HT). Many works focus on the structure/effects of a HT, while very few have demonstrated the viability of their HTs in silicon. Even fewer disclose how HTs are inserted or the time required for this activity. Our work details, for the first time, how effortlessly a HT can be inserted into a finalized layout by presenting an insertion framework based on the engineering change order flow. For validation, we have built an ASIC prototype in 65nm CMOS technology comprising of four trojaned cryptocores. A side-channel HT is inserted in each core with the intent of leaking the cryptokey over a power channel. Moreover, we have determined that the entire attack can be mounted in a little over one hour. We also show that the attack was successful for all tested samples. Finally, our measurements demonstrate the robustness of our SCT against skews in the manufacturing process.

A high-speed transient waveform sampling SCA ASIC prototype in 180 nm CMOS technology

Switched capacitor array (SCA) is an important method of waveform digitization in high-energy physics experiments. This paper presents the design and test results of an eight-channel SCA ASIC for high-speed waveform sampling. The ASIC is designed and fabricated in 180 nm CMOS technology. The sampling rate of up to 14.25 Gsps is achieved by adopting the proposed dual-chain interpolating delay cell in DLL. The ASIC can be configured to operate in two modes: long-chain mode for deeper sampling depth and ping-pong mode for recording two waveforms in a short time. The bandwidth is over 1.1 GHz. By optimizing the sampling order, the distortion caused by the bandwidth discontinuity is reduced. Deep N-well is adopted to isolate the interference between digital and analog signals. The test results show that the random noise is approximately 0.87 mV RMS after the fixed-pattern noise correction. The time resolution is better than 5 ps RMS over the time measurement range of approximately 73μs.

MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS high granularity timing detector

We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 °C shows negligible degradation over 16 days.

Design and performance of a 16-channel coarse-fine TDC prototype ASIC

This paper presents a prototype of a 16-channel Time-to-Digital Converter (TDC) based on the coarse-fine architecture for a small animal Position Emission Tomography (PET) system, which achieves both a large measurement range and high precision. The coarse time stamp is provided by two 12-bit counters, and the duplication of hardware is intended to avoid metastability when the hit signal edge is close to the edge of the counter clock. The fine time stamp is realized with a tunable delay line, which is adjusted by a 32-stage Delay-Locked Loop (DLL) and provides submultiples of the counter clock period. The device has been designed and fabricated in a 180 nm CMOS process. With a 200 MHz system clock, the full-scale measurement range is 20.48μs and the fine bin size is 156 ps. The test results show that the differential nonlinearity (DNL) is between −0.2 to ＋0.2 LSB, and the and integral nonlinearity (INL) is within the range of −0.5 to 0.2 LSB for all 16 channels. The one-shot time precision is better than 60 ps RMS. Power consumption of each channel is less than 8 mW.

The Q-Pix pixelated readout concept for future Liquid Argon Time Projection Chambers: status and prospects.

Future long baseline neutrino experiments such as the Deep Underground Neutrino Experiment (DUNE) pose challenges for development of readout techniques for multi-kiloton LAr Time Projection Chambers (TPCs). In contrast to wire/strip anode readout, a pixelated readout eliminates disadvantages such as disambiguation in 2D track reconstruction. The Q-Pix Consortium, established in 2019, is developing a pixelated readout technique for LAr TPCs based on charge-integrate/reset (CIR) circuits. The CIR blocks generate a sequence of reset pulses with time intervals corresponding to fixed charge integrals, allowing signal reconstruction without continuous digitization. The Q-Pix ASIC, intended for reading out pixel arrays, comprises CIR blocks along with digital components responsible for communication and reconfigurable data routing. This work is devoted to give an overview of the Q-Pix project, its status, and prospects, with emphasis on the development and prototyping of the Q-Pix readout ASICs.

Performance of radiation hard 3D pixel sensors for the upgrade of the ATLAS Inner Tracker

The Inner Detector of the ATLAS experiment at CERN will be replaced by a completely new Inner Tracker (ITk) to exploit the performance of the High Luminosity upgrade of the LHC accelerator (HL-LHC). The new detector will have to operate in an unprecedented radiation environment. In particular, the hybrid pixel detectors of the innermost layer of the ITk will be exposed to a particle fluence of about 1.7 × 1016 neq/cm2 before being replaced. A novel 3D pixel sensor technology featuring thin active substrates and small pixel cells has been selected to instrument the innermost barrel layer and rings of the ATLAS ITk. Prototypes of 3D pixel sensors produced at CNM in Barcelona, Spain, including 3D pixelated test structures as well as half-size sensors coupled to the RD53A ASIC prototype for HL-LHC, have been irradiated with protons and neutrons up to the radiation doses expected for the innermost layers of ITk. Their performance in terms of leakage current, power dissipation and hit efficiency of different pixel geometries after irradiation have been investigated and compared to the requirements for ITk.

ALICE - ITS3 — A bent, wafer-scale CMOS detector

ALICE is developing the ITS3 (inner tracker system) as upgrade of the inner layers of the presently installed ITS with the aim to improve the pointing resolution by factor of two and to lower the material budget to an unprecedented value of 0.05% X0 per layer.Its three layers are based on Monolithic Active Pixel Sensors (MAPS) thinned down to 20–40 μm. The configuration employs half-cylinders, which are bent around the beam pipe with bending radii of 18, 24 and 30 mm, respectively. The sensors are produced using stitching techniques allowing to reach a length of 28 cm. As consequence, the detector consists of six MAPS sensors only. The material budget is kept to a minimum using carbon foam elements to hold the stitched sensors in place, as well as by employing airflow cooling.This contribution summarizes the achieved R&D results on bending and thinning, the mechanical prototype, beam tests and the 65 nm prototype ASIC test, as well as the path towards the last remaining milestone, the implementation of a wafer-scale, stitched sensor design.

Measurement of single event effect cross section induced by monoenergetic protons on a 130 nm ASIC

Designing integrated circuits in radiation environments such as the High Luminosity LHC (HL-LHC) is challenging. Integrated circuits will be exposed to radiation-induced Single Event Effects (SEE). In deep sub-micron technology devices, the impact of SEEs can be mitigated by triple modular redundancy. The triplication of the most sensitive data is used to recover most of the data corruption induced by interacting particles. One type of SEE, called single event upset (SEU), is studied in this paper. The SEU cross-section and the performance of the triplication are estimated using an ASIC prototype exposed to a beam of protons. The SEU cross-section is measured and systematic difference between 1→0 and 0→1 bit flip rates is observed. The efficiency of the mitigation method is investigated.

Characterization and quality control test of a gigabit cable receiver ASIC (GBCR2) for the ATLAS Inner Tracker Detector upgrade

We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B through a 6 m Twinax AWG34 cable to lpGBT. GBCR2 also pre-emphasizes downlink command signals through the same electrical connection from lpGBT to RD53B. GBCR2 has seven uplink channels each at 1.28 Gbps and two downlink channels each at 160 Mbps. The prototype is fabricated in a 65 nm CMOS process. The characterization of GBCR2 has been demonstrated that the total jitter of the output signal is 129.1 ps (peak-peak) in the non-retiming mode or 79.3 ps (peak-peak) in the retiming mode for the uplink channel and meets the requirements of lpGBT. The total power consumption of all uplink channels is 87.0 mW in the non-retiming mode and 101.4 mW in the retiming mode, below the specification of 174 mW. The two downlink channels consume less than 53 mW. A quality control test procedure is proposed and 169 prototype chips are tested. The yield is about 97.0%.

Countermeasures against Static Power Attacks

In recent years it has been demonstrated convincingly that the standby power of a CMOS chip reveals information about the internally stored and processed data. Thus, for adversaries who seek to extract secrets from cryptographic devices via side-channel analysis, the static power has become an attractive quantity to obtain. Most works have focused on the destructive side of this subject by demonstrating attacks. In this work, we examine potential solutions to protect circuits from silently leaking sensitive information during idle times. We focus on countermeasures that can be implemented using any common digital standard cell library and do not consider solutions that require full-custom or analog design flow. In particular, we evaluate and compare a set of five distinct standard-cell-based hiding countermeasures, including both, randomization and equalization techniques. We then combine the hiding countermeasures with state-of-the-art hardware masking in order to amplify the noise level and achieve a high resistance against attacks. An important part of our contribution is the proposal and evaluation of the first ever standard-cell-based balancing scheme which achieves perfect data-independence on paper, i.e., in absence of intra-die process variations and aging effects. We call our new countermeasure Exhaustive Logic Balancing (ELB). While this scheme, applied to a threshold implementation, provides the highest level of resistance in our experiments, it may not be the most cost effective option due to the significant resource overhead associated. All evaluated countermeasures and combinations thereof are applied to a serialized hardware implementation of the PRESENT block cipher and realized as cryptographic co-processors on a 28nm CMOS ASIC prototype. Our experimental results are obtained through real-silicon measurements of a fabricated die of the ASIC in a temperature-controlled environment using a source measure unit (SMU). We believe that our elaborate comparison serves as a useful guideline for hardware designers to find a proper tradeoff between security and cost for almost any application.

Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium

We are presenting the experimental measurements of the power consumption and the maximum frequency in an ASIC prototype of 12 versions of the Trivium cipher: one standard version and two low power versions (FPLP and MPLP) with four different radix (radix-1, radix-2, radix-8 and radix-16). It is also described the mechanism for measuring power consumption in each Trivium implemented in the ASIC prototype. The clock tree of the ciphers has been designed in such a way that the clock signal of each Trivium can be cut independently. The experimental setup uses the Agilent 93000 testing system. The results show that the higher radix versions have a lower operating frequency and that the lower radix low-power versions have a very high power reduction. However, the Trivium radix-16 versions generate 16 bit/clock cycle so the measurements conclude that the MPLP version is the one with the lowest power consumption per bit (0.69 pJ/bit at 50 MHz).