Prototype Application-specific Integrated Circuit Research Articles

Design and measurements of SMAUG1, a prototype ASIC for voltage measurement using noise distribution

We present the implementation of the indirect voltage measurement using a noise distribution algorithm [1] in the prototype application-specific integrated circuit (ASIC) SMAUG_ND_1 designed in CMOS 28 nm technology. The chip implements the matrix of 7×7 pixels with the size of 68×68 μm. Each pixel contains eight independent comparators implementing the described algorithm and optional correlated-double-sampling method. The paper describes the ASIC architecture and briefly presents preliminary test results and encountered problems.

Design and Testing of a Prototype ASIC for the MTPC Readout at CSNS Back-n White Neutron Source

In this paper, a prototype Application Specific Integrated Circuit (ASIC) for the Multi-purpose Time Projection Chambers (MTPC) at Back-n White Neutron Source is presented. The ASIC integrates 16 readout channels and is fabricated in a 0.18 μm CMOS process. Each channel consists of a Charge Sensitive Amplifier (CSA), a Pole-Zero Cancellation (PZC), two bridged-T shapers, a baseline holder, and a fully differential output buffer. It provides selectable charge ranges of 2 pC and 10 pC, programmable peaking times from 110 ns to 1 μs, and an adjustable output common-mode voltage from 0.7 V to 1.25 V. The ASIC has already been tested and all the results meet the requirements. In the case of 100 pF input capacitance, 2 pC charge range, and 1 μs peaking time, it features a maximum Integral Non-Linearity (INL) of 0.48% and an Equivalent Noise Charge (ENC) of 0.749 fC, which makes the Signal-to-Noise Ratio (SNR) at full-scale input over 2600. In particular, a crosstalk rejection ratio of 63 dB is obtained in this prototype ASIC by using the baseline holder circuit in each channel to generate references for single-ended to differential conversion, isolating noise and crosstalk from the reference path.

Design and verification of a low-power AC/DC converter

Abstract This paper deals with the development and experimental verification of a low-power AC/DC converter. The proposed solution is aimed at the sub 0.5 W output power domain, commonly encountered in applications such as always-on wireless sensing nodes. To implement the proposed converter topology, a prototype application specific integrated circuit was designed and manufactured in a high voltage 0.35 µm CMOS technology, able to handle the maximum voltage of up to 120 V. The proposed design was first analyzed by transistor-level simulations showing high power efficiency and low no-load consumption of the developed converter. To facilitate experimental verification and measurement, an printed circuit board with the necessary external components was developed, as the available technology is unable to handle the AC line voltage directly. While the developed converter operated well with decreased input AC voltage, reliability issues arose during operation with the full AC line voltage of 230 Vrms. These are linked to digital control circuitry of the implemented chip and could be addressed in the second manufacturing run in the future.

Development of a front-end ASIC for silicon-strip detectors of the J-PARC muon [formula omitted]/EDM experiment

A front-end application specific integrated circuit (ASIC) with high rate capability and deep memory buffer is needed for the silicon-strip detector for the J-PARC muon g−2/EDM experiment. In this experiment, we reconstruct a positron track from muon decay by the silicon-strip detector and measure the muon anomalous magnetic moment and the electric dipole moment precisely to explore new physics beyond the Standard Model. The front-end ASIC is required to tolerate hit rates of 1.4 MHz per strip, to be stable to the change of hit rate by a factor of 150 from the beginning to the end of the measurement, and to have deep memory for the period of 40μs with 5 ns time resolution. To satisfy the experimental requirements, we designed a prototype ASIC “SliT128B” with the Silterra 180 nm CMOS technology. We report on the design and the performance of the SliT128B.

SENSROC12: A Four-Channel Binary-Output Front-End Readout ASIC for Si-PIN-Based Personal Dosimeters

A commercial silicon p-i-n (Si-PIN) photodetector is proposed for electronic personal dosimeters (EPDs) for the sake of the detection of low-energy X-rays and/or $\gamma $ -rays. Since the EPD is a portable device supplied with a battery, front-end electronics with small size and low power dissipation are required. This paper presents a fully-customized low-power front-end readout application-specific integrated circuit (ASIC) as a solution for this application. The ASIC includes four-channel analog front-ends with a digital interface. Each channel mainly includes a charge sensitive amplifier (CSA), a CR – RC 4 pulse shaper, an output buffer, a discriminator, and a digital-to-analog converter (DAC). An $I^{2}C$ interface and shift registers are designed to control the analog blocks. The modeling of equivalent noise charge (ENC) is discussed to optimize the circuit design. A prototype ASIC is designed in 0.35- $\mu \text{m}$ CMOS mixed-signal 3.3 V process. The die size is 2.4 mm $\times2.4$ mm. The preliminary test results are obtained. The input charge is 0.2–15 fC. The ENC is 119 e−+15.9 e−/pF under the power dissipation of about 1.25 mW/channel. The proposed ASIC can well meet the requirements of the EPD and other radiation detector systems.

Single Photon-Counting Pixel Readout Chip Operating Up to 1.2 Gcps/mm2 for Digital X-Ray Imaging Systems

This paper presents the design of a PXF40—an ultrafast single photon-counting (SPC) readout front-end electronics implemented in a CMOS 40-nm technology dedicated to hybrid pixel detectors. The prototype application specific integrated circuit core is a matrix of 432 pixels ( $24\times 18$ ) with a $100\,\,\mu \text {m}\times 100\,\,\mu \text{m}$ size. The single processing channel consists of a charge-sensitive amplifier (CSA), a discriminator, and a 24-bit counter with logic circuitry. The input signal is amplified and formed only by the CSA stage. Depending on the CSA input transistor current value, it can operate in two modes: FAST and FAST_HC with higher current. The measured power dissipation per channel $P = 45 \,\,\mu \text{W}$ and noise $\text {ENC} = 212\,\, \text {e}^{-}$ rms for the FAST mode, while $P=100\,\,\mu \text{W}$ and ENC = 185 e− rms for the FAST_HC mode, respectively. The readout chip can count up to 1.2 Gcps/mm2 based on 10% dead-time loss input rate parameter, which is currently the fastest SPC-based solution.

CDS circuit with BLA function for X‐ray CCD applications

Correlated double sampling (CDS) circuits are essential to process the X-ray charge-coupled devices (CCDs) that have been used in the modern X-ray astronomical field. A novel CDS circuit is presented. The innovation of the circuit is that it greatly improves the noise and linearity performances through moving the clamping switch out of the signal path as well as omitting the sampling switch which eliminates the nonlinearity and thermal noise introduced by these switches. Also, a baseline adjustment (BLA) circuit is incorporated so as to make efficient use of the dynamic range of the ADC, making the CDS circuit flexible to interface the CCD operating under a wide range of temperatures. A prototype application-specific integrated circuit (ASIC) is designed with GlobalFoundries 0.35 μm CMOS process and the experimental results show that with pixel rate varying from 100 kHz to 1 MHz, the integral nonlinearity and equivalent input noise performances are quite consistent, which are better than 27 ppm and 23 μV, respectively, within a dynamic range of 1.5 Vpp. The effective adjustment range of the BLA is at least 2 V, and the power consumption for a single CDS core is 10 mW approximately from a 3.3 V power supply.

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors**Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e− at zero farad plus 8.2 e− per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si).

Design of a Novel CMOS Front-End ASIC with Post Digital Shaping for CZT-Based PET Detector

This paper presents a novel front-end Application Specific Integrated Circuit (ASIC) dedicated to CZT detectors for positron-emission tomography (PET) imaging applications. The ASIC consists of a preamplifier using split-leg topology, a variable gain amplifier, a time-interleaved ramp ADC and a timing controller. The design techniques of these circuit blocks are discussed in detail. Meanwhile, the digital CR-RC shaping and the digital trapezoidal shaping are introduced as well. A prototype ASIC is implemented in CMOS $0.35~\mu \mathrm {m}$ process. The preliminary results have been obtained. The detection range of the gamma ray is from 11.2 keV to 550 keV. The non-linearity of the output voltage is less than 3%. The gain of the readout channel is 40.2 V/pC. The test results show that the proposed front-end electronics is appropriable for PET imaging applications.

Test of a 32-channel Prototype ASIC for Photon Counting Application.

A new low-power application-specific integrated circuit (ASIC) for Cadmium Zinc Telluride (CZT) detectors for single-photon emission computed tomography (SPECT) application is being developed at BNL. As the first step, a 32-channel prototype ASIC was designed and tested recently. Each channel has a preamplifier followed by CR-RC3 shaping circuits and three independent energy bins with comparators and 16-bit counters. The ASIC was fabricated with TSMC 0.35-μm complementary metal-oxide-semiconductor (CMOS) process and tested in laboratories. The power consumption is around 1 mW/ch with a 2.5-V supply. With a gain of 400 mV/fC and the peaking time of 500 ns, the equivalent noise charge (ENC) of 360 e- has been measured in room temperature while the crosstalk rate is less than 0.3%. The 10-bit DACs for global thresholds have an integral nonlinearity (INL) less than 0.56% and differential nonlinearity (DNL) less than 0.33%. In the presentation, we will report the detailed test results with this ASIC.

Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45keV to 281keV. The gain is larger than 100mV/fC. The equivalent noise charge (ENC) of the ASIC is 53e− at zero farad plus 10e− per picofarad. The power dissipation is less than 4.4mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200krad (Si).

A 4-Channel Waveform Sampling ASIC in 0.13μm CMOS for front-end Readout of Large-Area Micro-Channel Plate Detectors

Abstract We describe here the development of PSEC-3, a custom integrated circuit designed in the IBM-8RF 0.13 μm CMOS process and intended for fast, low-power waveform sampling. As part of the Large-Area Picosecond Photo-Detector (LAPPD) collaboration, this chip has been designed as a prototype application-specific integrated circuit (ASIC) for the front-end transmission line readout of large-area micro-channel plate photomultiplier tubes (MCP-PMTs). With 4 channels, PSEC-3 has a buffer depth of 256 samples on each channel, a chip-parallel ramp-compare ADC, and a serial data readout that includes the capability for region-of-interest windowing to reduce dead time. Chip calibrations and performance results, including achieved sampling rates of 2.5-17 GSa/s, are reported. Some design issues are identified, in particular the dependence of analog bandwidth on location in the sampling array. The causes have been found and addressed in a subsequent PSEC-4 submission.

Development of Waveform Multiplexing Method With Decay Time Modulation for Front-End ASIC of Pixelated Detectors

This paper proposes a novel waveform multiplexing method to realize high channel-density front-end application specific integrated circuit (ASIC) design. In the proposed method, multiplexing is achieved through connecting multiple preamplifiers to a single analog-to-digital converter (ADC). These preamplifiers have different decay time (90%-10%) which will be used as the tag information. The channel information can be identified by analyzing the decay time using digital signal processing. Based on this method, two prototype ASICs have been designed with 2-to-1 multiplexing. They are a 36-channel multiplexing charge sensitive preamplifier ASIC (MCSP) and a 24-channel multiplexing waveform sampling front-end ASIC (MWSFE).

Readout of scintillating plastic fibers with an APD array and prototype ASIC

We report on the development of custom front-end electronics for use with avalanche photodiode (APD) arrays as part of a NASA technology study for the readout of scintillating plastic fibers. APD arrays featuring 64 1 mm square pixels are used. We demonstrate that a pixel of these APD arrays coupled to relatively thin (0.25 mm) and short (15 cm) scintillating plastic fibers can be used to detect and measure the tracks of even minimum ionizing particles. An application-specific integrated circuit (ASIC) implementation of the electronics is required to produce a detector sufficiently compact for practical use in a space flight experiment featuring many thousands of channels. This paper briefly describes the detector concept and performance and presents the design and performance of a four-channel prototype ASIC fabricated using the 0.35 /spl mu/ Taiwan Semiconductor Manufacturing Company (TSMC) process.

Optimized cooling systems for high-power semiconductor devices

Straightforward air cooling of semiconductor devices has gradually been replaced by methods using liquid coolants, especially water cooling. In this paper, more advanced cooling devices for hockey-puck-type and module-type semiconductors are suggested. An established heat sink made of aluminum nitride for the water cooling of hockey-puck-type semiconductors has been used as a basis for the development of high-performance heat sinks for increased heat flux densities. By means of thermal and fluid dynamics simulation tools the internal geometry has been optimized with regard to improved heat transfer and reduced pressure drop. The simulation results have been confirmed by a number of experiments using various measuring techniques. As an alternative cooling method for semiconductor modules, a modified baseplate comprising a number of fins for direct water cooling has been suggested. For an intelligent temperature management control algorithms have been developed, resulting in a prototype application-specific integrated circuit which has been implemented for test purposes.

Possibilities for mixed mode chip manufacturing in EUROPRACTICE

EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

Designing a custom VLSI moment invariant data signal processor

This paper describes the design of a very large scale integration (VLSI) application-specific integrated circuit (ASIC) for use in pattern recognition. The ASIC implements a moment invariant engine for use in real-time pattern recognition. The pattern recognition scheme uses Hu and Maitra's algorithms for moment invariants. A prototype design was generated that resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain, which effectively incorporated the carry lookahead (CLA) function into the adder cells. The prototype ASIC was fabricated in a 2.0 μm CMOS technology (simulated at 20 MHz) and was tested with 100% success to 16.67 MHz. The prototype consisted of a 4 × 8 multiplier and an 11-bit accumulator stage. The present ASIC design consists of a 9 × 26 multiplier (that has a maximum propagation time of 50 ns) and a 48-bit accumulator stage. The final ASICs will be used in parallel at the board level to achieve the 232.5 megaoperations/s [1024 × 1024 operations/s = 1 megaoperations/s (MOPs)] necessary to perform the moment invariant algorithms in real time on 512 × 512 pixel images with 256 gray scales.

The ATM layer chip: an ASIC for B-ISDN applications

The authors describe the architecture of an experimental research prototype application specific integrated circuit (ASIC) designed to serve as a generic building block of the future broadband integrated services digital network (B-ISDN). The chip performs common asynchronous transfer mode (ATM) layer functions such as cell assembly and cell disassembly. A new media access control (MAC) protocol developed for a broadband customer premises network is also integrated in the chip. The chip interfaces to the B-ISDN through a synchronous optical network (SONET) synchronous transmission signal-3c (STS-3c) framer chip. The ATM layer chip has been designed using 1.2 mu m CMOS technology with a die area of 5.4*5.4 mm/sup 2/ and approximately 27000 transistors. Experimental results are described. At the user network interface, the chip can be used to implement broadband terminal adaptors and the network termination. At the broadband local exchange, the chip can be used in the implementation of ATM statistical multiplexers, ATM switch port controllers, etc.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>