Proposed Finite Impulse Response Filter Research Articles

Hardware Efficient Reconfigurable Digital Down Converter for Software Radio Receiver

ABSTRACT This paper describes a reconfigurable digital down converter (DDC) that can reduce the input sampling frequency from 128 MHz to an output of 1 MHz on a field-programmable gate array (FPGA) device. The proposed design employs a polyphase mixer followed by a half-band (HB) filter and a finite impulse response (FIR) filter. All the decimation filters involve polyphase architectures, enabling efficient hardware implementation. The polyphase mixer can reduce the high sampling rate frequency, and combining both HB and FIR filters results in a complex down-converted baseband spectrum. In addition, the modified HB filter reduces multiplier units, and the proposed FIR filter saves the delay elements. Using the optimal hardware description language (HDL) programming style, the design can further improve the area efficiency without sacrificing functionality. To evaluate the performance, the design has been implemented on the Kintex-7 Xilinx FPGA device. Experimental outcomes show that the proposed design significantly reduces hardware costs associated with other existing designs. Finally, a verification test certifies that the DDC has achieved a satisfactory spurious-free dynamic range (SFDR) of 115 dB. The high sampling rate and parallel processing capabilities of the proposed DDC make it an attractive solution for any software radio standard.

A FIR filter assisted with the predictive model and ELM integrated for UWB-based quadrotor aircraft localization

To improve the accuracy of the Ultra-Wide Band (UWB) based quadrotor aircraft localization, a Finite Impulse Response (FIR) filter aided with an integration of the predictive model and Extreme Learning Machine (ELM) is proposed in this work. The FIR filter estimates the quad-rotor aircraft ’s position by fusing the positions measured with the UWB and Inertial Navigation System respectively. When the UWB dada are unavailable, both the ELM and the predictive model are used to provide the measurements, replacing those unavailable UWB data, for the FIR filter. The ELM estimates the measurement via the mapping between the one step prediction of state vector and the measurement built when the UWB data are available. For the predictive model, we mathematically describe the missing UWB data. Then, both the measurements estimated with the ELM and predictive model are employed to estimate the observations via Mahalanobis distance. The test results show that the FIR filter aided by the predictive model/ELM integrated can reduce the Cumulative Distribution Function and position Root Mean Square Error effectively when the UWB is unavailable. Compared with the ELM assisted FIR filter, the proposed FIR filter can reduce the localization error by about 48.59 %, meanwhile, the integrated method is close to the method with a better solution.Graphical

FIR digital filter design based on improved artificial bee colony algorithm

The traditional swarm intelligence optimization algorithm is prone to fall into local optimal solutions in finite impulse response (FIR) digital filter design and has slow convergence speed. In order to optimize the design of FIR filter, a FIR digital filter design method based on improved bee colony (ABC) algorithm is proposed. This improved ABC algorithm can adaptively adjust the step size of the selected neighborhood of nectar source location. At the same time, the information of the global optimal solution is used to guide the search of candidate solution, which improves the global search ability of the algorithm. The improved ABC algorithm can balance the conflict between local search ability and global search ability, so it can achieve better optimization effect. The time and space complexity of the algorithm is analyzed in detail. Then, the improved ABC algorithm is used to design three typical FIR digital filters, namely low-pass, band-pass and band-stop filter. The performance of the designed filter is tested by simulation experiments. The experimental results show that compared with other state-of-the-art optimization algorithms, the proposed FIR filter design method has achieved better effect and performance. Meanwhile, the proposed design method has shorter optimization time. The superiority of the proposed method is verified.

FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier

ABSTRACT The energetic growth in portable multimedia and mobile communication system has increased the requirement of high-speed signal processing system with compact area and power consumption. Finite impulse response(FIR) filters are broadly used in image, signal, speech and video signal processing, medical electronics, noise filtering, mobile communication and many other fields. The performance of the whole signal processing system with FIR filter depends on the basic building block of multiplier and adders. Hence, the hybrid FIR filter is proposed to improve the speed of the signal processing system using hybrid adder and hybrid multiplier. In this technique, the basic hybrid adder is designed with the help of 2-bit adders, BEC and 4:1 Multiplexer. Also, the hybrid multiplier is designed based on partial products of two consecutive multiplicand bits which are added at same time using Han-Carlson, Weinberger and Ling adder. The proposed FIR filter is functionally verified and synthesised using Xilinx ISE simulator and is implemented in Spartan 6 FPGA boards. The result shows that the delay of FIR filter using the proposed multiplier is improved by 26.51%, 15.59%, 15.83% and 2.79% as compared with CLA, conventional CSA, CSA-BK-BEC and the proposed adder with array multiplier, respectively.

Design and Implementation of 6-Tap FIR Filter Using MAC for Low Power Applications

Abstract: A Significant number of mathematical operations, such as multiplication and accumulation, are often required by a digital signal processing (DSP) algorithm. Many DSP applications have latency limitations, which mean that the DSP operation must be performed within a certain amount of time for the system to function, and because DSP gives high accuracy, filters constructed in DSP have tighter control over the output accuracy. As a result, DSP applications must be fast, have a high throughput, and use little power. Filters with a finite impulse response (FIR) are commonly employed in digital signal processing (DSP) applications. A FIR filter that is efficient in terms of electricity is being built. The multiplier and accumulator (MAC) unit used a new implementation approach to develop this system. FIR filter is a type of filter. Multipliers, adders, and a variety of other components are commonly used in FIR filters. Multipliers, adders, and a series of delays are used to form the filter's output in FIR filters. The goal of this project is to design and implement a 6-tap finite impulse response (FIR) filter by replacing multipliers with an 8-bit Multiplier and Accumulator (MAC) unit within the FIR filter, where a low-power MAC unit is always a key to achieving high performance in a DSP system, and D flip-flops are used in place of delays and constructed using a latch-based design. The Wallace tree Multiplier was utilised in the construction of the MAC unit because it reduces the amount of partial products, and the adders used for accumulation are half adders and full adders. In the FIR filter, for the purpose of summing This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx Vivado 2018.1 software environment and the implementation is done using VHDL codes. The result analysis shows that the proposed FIR filter consumes low power than conventional (standard) FIR filter. As the dynamic power results up to 11.932W and after implementation it results up to 12.029W. Keywords: MAC, Low power, latch-based design.

LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION

Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

Performance analysis of Low energy and highspeed DA-RNS based FIR filter design for SDR Applications on FPGA

For different applications, the Finite Impulse Response (FIR) filter is widely used in digital signal processing (DSP) applications. We exhibit a significant Residue Number System (RNS)-based FIR filter design for Software Defined Radio (SDR) filtration in this article. Including its underlying concurrency and information clustering process, the RNS provides important statistics over FIR application in specific. According to several residue computing and reverse translation, expanded bit size results in a significant performance trade-off, conversely. Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed in this study, which involves distributed arithmetic-based residue processing. To execute the task of reverse translation and to store pre-computational properties, the suggested Residue Number System architecture makes use of built-in RAM blocks found in field-programmable gate array (FPGA) devices. The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque. Followed by FPGA hardware synthesis for different input word sizes and FIR lengths verification by the efficiency of the FIR filter core, fetal audio signal detection is performed first. The test results reveal that over the optimization procedure RNS method, a compromise in traditional RNS FIR over filter size is narrowed, as well as a substantial decrease in sophistication.

FPGA Implementation of high speed-low energy RNS based Reconfigurable-FIR Filter for Cognitive Radio Applications

The Finite impulse response (FIR) filter is prominently employed in many digital signal processing (DSP) systems for various applications. In this paper, we present a high-performance RNS based FIR filter design for filtration in SDR applications. In general, the residue number system (RNS) gives significant metrics over FIR implementation with its inherent parallelism and data partitioning mechanism. But with increased bit width cause considerable performance trade-off due to both residue computation and reverse conversion. In this paper optimized Residue Number System (RNS) arithmetic is proposed which includes distributed arithmetic based residue computation during RNS multiplication followed by speculative delay optimized reverse computation to mitigate the FIR filter trade-off characteristics with filter length. The proposed RNS design utilizes built-in RAMs block present in the devices of FPGA to accomplish the process of reverse conversion and to store pre-computational values. A distinctive feature of the proposed FIR filter implementation with core optimized RNS is to minimize hardware complexity overhead with the improved operating speed. Initially, fetal audio signal detection is carried out to validate the functionality of FIR filter core and FPGA hardware synthesis is carried out for various input word size and FIR length. From the experimental, it is proved that the trade-off exists in conventional RNS FIR over filter length is narrow down along with considerable complexity reduction with our proposed optimized RNS system.

Design of FIR filter ISOTA with the aid of genetic algorithm

The field of digital signal processing has been receiving justified attention over the years because of a number of reasons including sophisticated algorithms, high computational speed and wider area of applications. In connection to this, design of finite impulse response (FIR) filter has drawn the attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this paper, a new technique of FIR filter design has been addressed by virtue of genetic algorithm. Filter coefficients have been searched over the discrete space in such a way that the architecture consists of shifts and only two adders. As a matter of fact, the proposed FIR filter involving shift and only two additions (ISOTA) results in minimal hardware cost during its implementation. This has been illustrated by means of a few example filters in this work. Some of the recently proposed FIR ISOTA filters have also been taken for the purpose of comparison. Finally, the proposed filter has been implemented on Altera Cyclone IV FPGA board.

EEG Processing Using VHBCSE Based FIR Filter

There is a major role for filter in noise removal. because of simple structure, stationary response and adaptively with embedded microprocessors. The Finite Impulse Response (FIR) filter has many advantages on signal processing . to process the Electroencephalography (EEG) signal the FIR filter is the best suited option. The noise in the EEG signal can reduced by using FIR filter. The hardware complexity of FIR filter is high because of multipliers present in the FIR filter. By reducing the multipliers fast and less area using FIR filter is obtained. This paper present a vertical and horizontal Binary common subexpression elimination (VHBCSE) algorithm based FIR filter to process the EEG signal. The common subexpression elimination (CSE) algorithm eliminate the bit patterns which are often occurring. The proposed FIR filter reduce noise of EEG signal rapidly ,by consuming less power and design only required less area. Xilinx ISE design suite 14.7 is used to simulate the FIR filter in FPGA and the MATLAB environment is to generate the EEG signal.

시변 이산 선형 시스템에 대한 지수가중 유한 임펄스 응답 필터

In this paper, an exponentially weighted Finite Impulse Response (FIR) filter is proposed for discrete-time linear time-varying systems. The weighting method of measurements was first introduced for the FIR structured estimators, then an optimal design of the exponentially weighted FIR filter was developed with respect to a minimum variance criterion for discrete-time linear time-varying systems. The proposed filter is designed to be unbiased and independent of initial state information. Due to the inclusion of the weighting factor, it is expected to be less prone to model uncertainty and numerical errors than the conventional optimal FIR filter. Moreover, the proposed FIR filter is reduced to the optimal time-varying FIR filter with an equal weight, and can thereby provide a more general solution than the conventional optimal FIR filter. Through a numerical study, the performance of the proposed FIR filter was shown by comparing it with the exponentially weighted Kalman filter and the conventional optimal FIR filter when the modeling uncertainties exist.

An Improved VLSI Design of the ALU Based FIR Filter for Biomedical Image Filtering Application.

FIR filter is the most widely used device in DSP applications, which is also applicable to integrate with image processing approaches. The ALU based FIR structure is applicable for various devices to increase the performance. The ALU design operation includes accumulation, subtraction, shifting, multiplication and filtering. Existing methods are designed with various multipliers like Wallace tree multiplier, DADDA multiplier, Vedic multiplier and adders like carry select adder, and carry look-ahead adder. The main objective is to reduce the area, delay and power factors since optimum VLSI circuit is employed in this paper. By these adders and multipliers, operations are independently enabling main operations in DSP. The FIR filter is designed using a MAC unit with clock regenerative comparators. In the field of the VLSI industry, the low power, reduced time, and area-efficient designs are mostly preferred for various applications. Adders and multipliers play a vital role in VLSI circuit designs. The recent electronics industry uses a digital filter for various real-time applications. This utilizes Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters, here the FIR filter is most stable than IIR filter. This FIR filter indicates the impulse signal into finite form and it is used mainly in DSP processors for getting high-speed. In these two ALU and FIR circuits, the adders and multiplier block's usage is increased, it consumes much power. The proposed research work uses the clock-gating technique for reducing power consumption. Here the latch-based clock gating technique provides an efficient result. XOR-based logic circuit reduces the design complexity and utilizes the less area. Carry save accumulator is a digital adder used for addition. It provides the two set of output, which is partial sum and carry output. The ripple carry adder uses a full adder circuit for its operation. It propagates the carry value in the last bit. In addition, the combination of CSA and RCA utilizes less area, high speed and provides the better throughput. In multiplier block, the booth multiplier algorithm is used with XOR-based logic. Here this proposed FIR filter is designed for performing image filtration of retina image. This process improves the better visualization approach inthe medical field. Thus, the proposed ALU based FIR filter with a latch-based clock gating technique is designed and analyzed with various parameters. Here the modified adders and multipliers are proposed for the efficiency of the system. The modified carry save adder is proposed with combining ripple carry adder logic for improving the adders' performance. The enhanced booth multiplier is designed using add and shift method for reducing the numberof stages to calculate the result. This process is applied to perform image processing of the retina image. After designing the ALU based FIR filter structure in the VLSI environment, the image is loaded on the MATLAB as the .png format, then it is converted into a hex file, which is read from the Xilinx to perform filtering the process. Then the 'dataout' is converted into a binary file to obtain the result of the filtering process. The enhanced booth multiplier reduces the delay by reducing the number of stages to calculate the result. Here the clock gating technique is proposed with the latch-based design for reducing the dynamic and clock power consumption. The number of adder's circuit in both ALU and FIR circuits is less since it improves the overall efficiency of the system. Thus, the proposed methodology concluded that the design and analysis of ALU based FIR filter for medical image processing give the efficient result on the way of achieving the factors such as power (Static & Dynamic), Delay (Path delay) area utilization, MSE and PSNR. Here the image processing of FIR results to MSE and PSNR values, which obtained a better result than the existing VLSI based image processing works. The latch-based clock gating circuit is connected with the proposed circuit, based on the gated clock signal, it optimizes the gated circuit of the whole design since it also reduces the error and provides the efficient power report. This proposed VLSI model is simulated using Xilinx ISE 14.5 and Modelsim synthesizes it; here with the help of MATLAB, with the adaptation of the 2018a tool, the image filtering was done.

High speed low area OBC DA based decimation filter for hearing aids application

This brief presents a decimation filter for hearing aid application using distributed arithmetic (DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA based finite impulse response (FIR) filter with a shared look-up table (LUT) updating scheme. The size of the LUTs in DA increases exponentially with the order of filters. Shared LUT based DA structure is a solution to reduce this large memory requirement for higher order filters. The proposed shared LUT updating scheme uses LUT partitioning in which coefficients are spilt into small length vectors and it ensures a drastic reduction in the size of LUTs. The proposed DA filter is synthesized on CMOS 90 nm technology using Synapsis ASIC Design Compiler. The proposed design achieves high speed at a reduced area-delay product (ADP) when compared with recent designs. The proposed architecture is implemented and tested on Virtex 5vsx95-1ff1136 FPGA and the results show that the proposed design involves less number of slices and offers high speed than existing designs. A three-stage decimation filter of hearing aids is designed with the proposed FIR filter and is implemented on the target device by Matlab simulink and Xilinx system generator.

Experimental setup of stretchable arid dry pad sensors for the signal acquisition fir filter design using Vedic approach

At present in Medical Image processing a hard point to settle any issue with the assistance of Computer collaborator using Arid-dry pad sensor plays a prominent role. Specialist is to investigate the medical diagnosis with the assistance of imaging system such as The CT scan, MRI scan, EEG, Ultrasound technique or any kind of medical images analyzing the system of the patient with the help of images. Design of low power and low delay digital finite-impulse response (FIR) which plays a vital role in medical image applications along with Arid-dry pad sensors. These days, there are numerous versatile applications requiring low power and high throughput than any time in recent memory. In this research the FIR channel framework configuration has turned into a huge execution objective. The Finite Impulse Response (FIR) Filter is the vital segment for planning a medical image processing. The adders and multipliers play an important role in FIR filter while considering these, not only the fast response but also the number of component, area and path delay. The proposed FIR filter is designed by using adder and Wave pipelined Vedic multiplier from the analysis of various adders and multipliers. The Wave pipelined Vedic multiplier performs multiplication process in a hierarchical manner. The work has demonstrated the effectiveness of Urdhva Triyagbhyam– Vedic technique for multiplication which strikes a distinction in the real procedure of increase itself. It empowers parallel age of moderate items, wipes out undesirable increase ventures with zeros and scaled to higher bit levels. Thus, the proposed method can minimize the setup time violation and path delay of the FIR filter with pad sensors. The proposed FIR Filter is simulated, synthesized, calculating power consumption using ISE simulator, Xilinx and Altera Quartus II.

Implementation of FIR filter using reversible modified carry select adder

SummaryAny arithmetic operation can be performed using the method of Reversible process which allows minimum arithmetic execution. An essential scenario for achieving this condition is the arithmetic design connections should be of one to one. The Finite Impulse Response (FIR) Filter is that the indispensable part to design digital signal processing framework. The adders and multipliers assume an urgent part in FIR filter while thinking about the power. In this paper, an effective FIR filter is actualized utilizing minimum power reversible modified SQRT carry select adder utilizing Brent Kung adder and D latch. Reversible logic has developed as another outline method to the customary rationale, prompting low power consumption and lesser circuit region. For accomplishing low power, reversible rationale method of task is implemented inside the style. The proposed configuration accomplishes three‐overlap benefits in terms of Area‐power‐delay. From the combination comes about, the newly portrayed minimum power FIR filter configuration shows low power of 294641.397 nW when contrasted with regular outline. Proposed FIR Filter is reenacted by utilizing rhythm device as cadence tool.

A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS

Thanks to the high flexibility in matching the channel frequency response and the compatibility with simple adaptation techniques, Finite Impulse Response (FIR) filters enhance the equalization performances of high-speed wireline receivers. This paper presents a 25-Gb/s FIR equalizer in 28-nm CMOS. The impact of filter noise and distortion, crucial aspects for an analog implementation, is discussed. A thorough system analysis, aimed at deriving the specifications for circuits design, suggests four taps, with a tap-to-tap delay in the range 0.5-1 UI, as optimal compromise among complexity (hence power dissipation) and equalization performances. To keep high SNR, a new all-pass stage is proposed to realize a delay line suitable for high-speed operation while being able to accommodate large input signal amplitude. Measurements are shown at 25 Gb/s for both Non Return to Zero (NRZ) and Pulse Amplitude Modulation (PAM)-4 signals. With a core power dissipation of 25 mW from 1-V supply, the proposed FIR filter recovers 20- and 9-dB channel loss for NRZ and PAM-4, respectively, with horizontal eye openings of 50% and 30%. Compared with the previously reported FIR filters for wireline links at comparable speed, the proposed realization achieves excellent equalization performance with the best power efficiency of 1 mW/Gb/s.

An Efficient Low Power and High Speed Distributed Arithmetic Design for FIR Filter

Background/Objectives: FIR filters play a vital role in signal processing applications. This research work presents a low power and high speed efficient buffer based Distributed Algorithms and it is analyzed with Electro Cardio Gram (ECG) signal Finite Impulse Response (FIR) filter design. Methods/Statistical Analysis: The proposed FIR filter is designed using buffer based DA and it is simulated and synthesized using Cadence digital labs. This is compared with different architectures such as conventional DA, separated look up table DA and LUT less DA. Findings: Synthesis report shows that the proposed design has 52% less power dissipation compared with the conventional DA, 21% reduction in delay with separated Look Up Table (LUT) DA and 8% reduction in area with LUT less DA. Conclusion/Improvements: Presently this method is applied for ECG signal input with 16-tap FIR filter. This can be extended for higher order filters to achieve better performance.

Optical micro-multi-racetrack resonator filter based on SOI waveguides

In this paper, we present a new design of optical Finite Impulse Response (FIR) filter based on combination of multi-racetrack resonators realized with Silicon waveguides. Numerical investigations were carried out on the spectral response of the proposed filters design, in order to obtain FIR band-pass filter around the photonic carrier wavelength of 1.55μm. The proposed FIR filter was fabricated using electron beam lithography (EBL). The device was preliminary experimentally examined by a combination of scanning electron microscopy (SEM) and atomic force microscopy (AFM).

A minimum variance FIR filter with an [formula omitted] error bound and its application to the current measuring circuitry

In this paper, we propose a minimum variance finite impulse response (FIR) filter with a guaranteed H∞ error bound. The proposed FIR filter is required in advance to make use of only inputs and outputs on the recent finite time so that its impulse response has a finite duration, or it has finite memory with respect to past data. From such requirement, a transfer function from the external noises to the estimation error is first obtained, and then the corresponding estimation error variance is minimized with respect to the filter gains while keeping its H∞ norm bounded. The constrained minimization problem is represented with linear matrix inequalities (LMI) that can be efficiently solved using convex programming techniques. It is shown through application to the current measuring circuitry in the magnetic levitation system that the proposed FIR filter is more robust against temporary uncertainties than an existing mixed H2/H∞ IIR filter with a guaranteed H∞ error bound.

Revisiting the doppler filter of LEO satellite GNSS receivers for precise velocity estimation

The theoretical aspects of the precise velocity determination of Low Earth Orbit (LEO) satellites’ onboard Global Navigation Satellite Systems (GNSS) receivers are derived. It shows that the receiver’s Phase Lock Loop (PLL) is required to feature extremely small group delay within its low frequency band, which is in contrast to existing work that proposed wide band linear phase filters. Following this theory, a Finite Impulse Response (FIR) filter is proposed. To corroborate, the proposed FIR filter and an Infinite Impulse Response (IIR) filter lately proposed in literals are implemented in a LEO satellite onboard GNSS receiver. Tests are conducted using a third party commercial GPS signal generator. The results show that the GNSS receiver with the proposed FIR achieves 11 mm/s R.M.S precision, while the GNSS receiver with the IIR filter has a filter-caused velocity error that can not be ignored for space borne GNSS receivers.