Proposed Clock Generator Research Articles

A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design

This article presents a programmable multiple frequencies clock generator with a process and temperature compensation circuit design. The proposed clock generator can achieve a stable and wide frequency range output for a single input frequency by using digital control codes as well as process and temperature compensation mechanisms. In our approach, the first step is to adjust the duty-cycle of the input clock by using a digitally controlled pulsewidth modulator (DCPWM) to generate an output clock signal with a duty-cycle of 20% to 80%. Second, the various duty-cycle clock outputs of the DCPWM are integrated by the duty-cycle-to-voltage converter to generate analog voltage signals to control the succeeding voltage-controlled ring oscillator (VCO). Through the use of various control voltages, different VCO output frequencies are generated. Finally, by using the process and temperature compensation circuit, the proposed clock generator can provide a stable and wide frequency range. The proposed chip is fabricated in a 180-nm CMOS process and has an output frequency range of 35–138 MHz at a supply voltage of 0.9 V. At 120 MHz, the power dissipation and rms jitter are 224.3 μW and 7.84 ps, respectively. The active area of the chip is 0.62 mm × 0.76 mm.

0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop

This brief presents a quadrature resonant clock generator for driving four 4.3-mm load wires with tuning capacitors and an amplitude control feedback loop. By using frequency tuning capacitors, which reduce the mismatch in operation and LC resonant frequencies, the proposed clock generator offers power reduction by 20-25% compared with conventional CMOS clock driver and by 23-34% compared with conventional CML clock driver over a wide voltage swing. The amplitude control feedback loop, which determines the bias current of the negative gm cell, maintains the constant optimized clock swing over wide PVT variations. Measurement result from the prototype chip fabricated in 65 nm CMOS shows that total power consumption of the proposed quadrature resonant clock is 11.92 mW in 7-GHz operation with four 559-fF load wire capacitances. Measured period jitter is 573.6 fsrms and phase noise at 1MHz offset is -138.37 dBc/Hz.

A small area DLL-based clock generator using duty cycle controllable cyclic VCDL

ABSTRACT A small area DLL-based clock generator is presented in this work. To reduce the chip area and generate the high-frequency clock, a new cyclic voltage controlled delay line (VCDL) is used. The new VCDL not only provides multiple output frequency but also with duty cycle controllable output. Compared with the traditional VCDL, it has the advantage of the small chip area and low power consumption, and is suitable for use in the frequency multiplier of the digital system. The proposed clock generator has been fabricated in TSMC 0.18 µm complementary metal-oxide-semiconductor process. The core area of the proposed clock generator is 0.018. The measure root-mean-square and peak-to-peak jitters are 2.66 ps and 24 ps at 500 MHz, respectively. The phase noise is about −106.36dBc/Hz at the offset frequency of 1 MHz. The power dissipation is 7.2 mW for a supply voltage of 1.8 V.

A Low-Power Clock Generator with a Wide Frequency Tuning Range and Low Temperature Variation: Analysis and Design

This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit analysis. Post-layout simulation results of the proposed clock generator in 180[Formula: see text]nm CMOS technology are also presented. It exhibits a wide tuning range of 807 MHz to 2.66 GHz. The phase noise of the output signal is about [Formula: see text][Formula: see text]dBc/Hz at 10[Formula: see text]MHz offset frequency. Frequency changes less than [Formula: see text] in the temperature range of [Formula: see text]C–[Formula: see text]C. The clock generator consumes 0.657[Formula: see text]mW of power. Results show improvement in comparison to the previous works.

A programmbale 8-channel multiphase clock generator with 360 phases for focus ultrasound applications

An area efficient, programmable multichannel, multiphase clock generator is proposed to improve the phase resolution for focus ultrasound applications. By using the proposed phase-folding method, the cell amount for generating 360 phases are reduced from 360 to 38 cells. The proposed clock generator is able to provide 360 phases in real-time with 1° phase resolution, 1–51.9% 6-bit DPWM for each channel, and which output frequency varies from 0.1 to 1.5 MHz. Due to the proposed multiphase system is a real-time system, many independent multichannel applications such as focus ultrasound could easily adopt the proposed structure. A new phase-error calibration method for PLL is also present in this paper for reducing the static phase-error due to process voltage and temperature variation. It improves the accuracy of the phase difference in the multiphase system. The proposed ASIC was fabricated in a standard 0.18 μm CMOS process. Measured result shows that multiphase clock generator is able to provide 360 selective phases for each channel. The derived DNL is from −0.106 to +0.108 LSB, and the INL is from −0.284 to +0.449 LSB at 1 MHz.

A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique

In this paper, a fast-lock low-power all-digital delay-locked-loop (ADDLL)-based clock generator is proposed that generates fractional multiples of a reference frequency. The proposed clock generator comprises an ADDLL with dual-loop architecture and a fractional frequency multiplier. The coarse tune loop and fine tune loop of the proposed ADDLL can achieve a fast locking time and decrease the static phase error. Moreover, the proposed frequency multiplier can synthesize the 28-phase output clocks of the ADDLL to achieve high multiples. The experimental results demonstrated that the output frequency range of the proposed clock generator was between 176 and 224 MHz, with multiplication factors of 11 ×, 11.5 ×, 12 ×, 12.5 ×, 13 ×, 13.5 ×, and 14 × to cover the very high frequency (VHF) frequency band, where every channel had a bandwidth of 8 MHz. Moreover, the output duty cycle was close to 50% because a divider was used to generate the output signal and the lock time was less than 20 clock cycles. The clock generator was fabricated using a 0.18-μm standard CMOS process, with an active area of 0.59 mm2, power dissipation of 6.7 mW at 224 MHz, and phase noise of − 94.33 dBc/Hz with an offset of 1 MHz. Furthermore, at 176 MHz, the root-mean-square jitter was 25.01 ps, which was less than 0.45% of the output period.

A Continuous Sweep-Clock-Based Time-Expansion Impulse-Radio Radar

This paper presents a single-chip impulse-radio (IR) radar transceiver that utilizes a novel continuous sweep-clock generator. While requiring low power and small area, the proposed clock generator enables a versatile IR radar operation with millimeter resolution. The radar detection range and update rate are adjustable by an on-chip delay command circuit or by an external master. The IR radar transceiver, working with transmission and reception clocks, incorporates a spectrum adjustable transmitter and a wide-band sampling receiver. The recovered echo pulses from the radar are distinguishable in an expanded time scale. For the first time, generalized analyses on the radar range for time-expansion IR radars are established. The single chip radar transceiver is fabricated in a 130-nm CMOS technology occupying a chip area of 1.0 mm2. The measurements show that the echo pulses are recovered with a millimeter range resolution, while dissipating 30 mW. Respiration motions are successfully captured with the prototype radar.

Wide-range CMOS reference clock generator with a dynamic duty cycle scaling mechanism at a 0.9-V supply voltage

This paper presents a wide-range CMOS reference clock generator with a dynamic duty cycle scaling mechanism. A new duty-cycle-to-voltage converter (DCVC) is proposed for the clock generator, which requires only the duty cycles of differential 25-MHz input signals. When these duty cycles are set into the DCVC, dual control voltages, namely VP and VN with positive and negative control duty cycle coefficients, respectively, are produced to manage the current sources of the differential voltage-controlled ring oscillator and supply a wide range of frequency channels. The proposed clock generator can supply a stable output clock with a wide range of frequencies from 37 kHz to 34 MHz. Notably, the wide-range CMOS reference clock generator can also be used in a universal serial bus hub or in wide band applications with low supply voltages and small areas.

2.5 mW 2.73 GHz non‐overlapping multi‐phase clock generator with duty‐cycle correction in 0.13 µm CMOS

A high-speed low power multi-phase clock generator with a simple duty-cycle correction circuit is presented. By adding tail transistors driven by the out-phase signal as a discharge path to correct the phase overlapping in the conventional design, 25% duty cycle multi-phase clocks are obtained with <1° phase error. Thanks to this simple topology, the proposed work is featured with fast-speed, low power with a small silicon area. Fabricated in a 0.13 µm RF CMOS process, the proposed clock generator has a measured operating frequency up to 2.73 GHz with a maximum power consumption of 2.5 mW from a 1.2 V supply.

A 1.1 V 10-bit 62MS/s pipeline ADC with two-step non-overlapping clock generation for multi I-Q channel RF receivers

A multi-channel pipeline analog-to-digital converter (ADC) with two-step non-overlapping clock generation is presented. Op-amp sharing and reference buffer sharing between channels are implemented without a front-end sample-and-hold amplifier for low power consumption. The proposed clock generator can easily implement short reset phases between non-overlapping clocks to remove the memory effect from opamp sharing. The prototype 4-channel ADCs are implemented in a 0.11 μm CMOS process. The 10 bit ADC achieve 56.6 dB (9.1 bit ENOB) SNDR and 72.2 dB SFDR with 3 MHz input frequency. Each ADC slice occupies 0.4 mm2 and consumes 13 mW at 62 MS/s sampling frequency under 1.1 V supply.

Programmable fractional‐ratio frequency multiplying clock generator

A new programmable delay-locked loop (DLL) based fractional frequency multiplying clock generator is presented. In contrast to conventional DLL-based clock generators that generate only integer clock multiplication, the proposed clock generator provides fractional-ratio frequency multiplication while maintaining the advantages of DLLs, such as the deskewing between the input and the output clocks. Implemented in a 0.13 μm 1.2 V CMOS process, the proposed clock generator achieves an effective peak-to-peak jitter of 7.5 ps and occupies an active area of 0.018 mm 2 while dissipating 9.0 mW at 1.5 GHz. The output frequency ranges from 0.85 to 1.5 GHz with programmable fractional multiplication ratios of N / M , where N = 4, 5, 8, 10 and M = 1, 2, 3.

480 MHz 10‐tap Clock Generator Using Edge‐Combiner DLL for USB 2.0 Applications

A clock generator with an edge‐combiner DLL (ECDLL) has been developed for USB 2.0 applications. The clock generator generates 480 MHz 10‐tap output signals from a 12 MHz reference signal and consists of three DLLs to shrink the design area so that it is smaller than a conventional one based on a PLL. Each DLL is applied to our proposed shot pulse reset technique to prevent from a harmonic lock and is applied to a voltage‐controlled delay line (VCDL) with a trimming function to operate against any process voltage temperature (PVT) variations. A 90 nm CMOS process was used to fabricate our proposed clock generator. The 480 MHz 10‐tap output signals satisfy the USB 2.0 specifications. A power consumption is less than 1.3 mW and a locking time is less than 3.5 μs, which are far less than a conventional one, 10.0 μs. The design area is 200 × 225 μm, which is half that of the conventional one.

Design of Low-power Clock Generator Synchronized with the AC Power Source Using the ADCL Buffer for Adiabatic Logics

In this paper, the low-power clock generator synchronized with the AC power signal using the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the ADCL, the clock signal of logic circuits should be synchronized with the AC power source. The clock signal for an adiabatic charging and discharging with the AC power signal was generated with the designed Schmitt trigger circuit and ADCL frequency divider using the ADCL buffer. From the simulation result, the power consumption of the proposed clock generator was estimated with approximately 1.181uW and 37.42uW at output 3kHz and 10MHz respectively.

An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme

In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.

A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications

This brief presents an all-digital synchronous clock generator with an open-loop architecture, which achieves a fast lock and a wide range for mobile applications. The proposed architecture based on a clock-synchronized delay adopts a multipath delay line, which provides a high resolution and a low deterministic jitter with calibration circuits. A frequency range selector with a locking range moving technique achieves a wide-range operation. The proposed clock generator operates from 100 MHz to 1 GHz with a 14-ps peak-to-peak jitter performance at 1 GHz. The measured lock time is three to ten clock cycles depending on the operating frequency. The clock generator is implemented in a 0.18-μm CMOS process.

개선된 자동 주파수 보정회로를 이용한 광대역 클록 발생기 설계

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350㎒, and a VCO frequency is 270㎒. The lock time of clock generator is less then 3us at input reference frequency, 67.5㎒. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1㎽ at 1.8V supply and layout area is 0.384㎟.

A DLL based clock generator for low-power mobile SoCs

In this paper, a delay locked loop (DLL) based clock generator is proposed. In this DLL, a dual edge triggered phase detector (DET-PD) with a high phase detector gain, a wide phase capture range, and a reduced reset time is proposed in order to achieve fast lock speed without degrading the loop stability. To resolve the static phase offset problem of previous DET-PDs, a feedback based duty cycle controller is proposed. A high speed frequency multiplier is also proposed in order to achieve a high operating frequency and a wide operating range. The proposed DET-PD shows a 4.19 ps static phase offset at a typical corner, which is 10.5 times better than that of the conventional DET-PD based DLL, and shows a 2.36 - 2.51 times improved lock speed compared with a single edge triggered phase detector (SET-PD) based DLL. Also, the proposed clock generator achieves an operating range of 150 MHz - 2 GHz and frequency multiplication factor of x1 - x8.

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock

A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-mum CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-.MU.m CMOS

This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13µm CMOS process achieves 105MHz to 225MHz of clock frequency while consuming 4.2mW from 1.2V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8ps and 0.031% at 105MHz, respectively.