Proportional Absolute Temperature Research Articles

A high PSRR bandgap voltage reference with piecewise compensation

This paper describes an alternative high power supply rejection ratio (PSRR) bandgap voltage reference (BGR) circuit with piecewise compensation. A proportional to absolute temperature (PTAT) current structure with high loop gain is adopted to achieve high PSRR, a current proportional to absolute temperature square (PTAT2) circuit is used to implement the temperature piecewise compensate. Experimental results of the proposed BGR implemented in a 0.5 ​μm CMOS process demonstrate that a PSRR of 83 ​dB is achieved, and a temperature coefficient (TC) of 8.83 ​ppm/°C over a temperature range of 165 ​°C (−40 ​°C–125 ​°C) is realized.

A compact and energy-efficient ultrasound receiver using PTAT reference circuit

Portable and embedded ultrasound applications require energy-efficient receivers that can operate over a wide range of incident ultrasonic energy. In this paper we show that by directly injecting the ultrasonic signal into a proportional-to-absolute-temperature (PTAT) reference circuit, the pre-amplification and rectification stages used in a conventional ultrasonic receiver can be eliminated which leads to a significant improvement in the system energy-efficiency. The PTAT circuit self-biases itself in accordance to the magnitude of the incident ultrasound pressure signal and is also configured to function as an active diode (with threshold voltage of ≈25 mV) to achieve signal rectification. In this paper we present measurement results obtained from a PTAT-based ultrasound receiver that has been prototyped in a 0.5 μm CMOS process, and we compare the performance to a standard transconductance amplifier (TCA) based design that has also been prototyped in the same process. The improvement in input dynamic range was measured to be 25 dB and sensitivity of the PTAT-based receiver was measured to be 21 Hz/mV when the biasing current is 16.67 nA. We also present the bit-error-rate (BER) performance when the receiver circuit is used for a substrate communications application where ultrasound is used for transmitting and receiving data through an Aircraft grade Aluminum plate.

A RF PVT Compensated Negative Resistance Circuit for Q-factor Improvement of Passive Elements in CMOS

A RF process, voltage and temperature (PVT) compensated negative resistance (NR) circuit is proposed to improve the quality factor (Q-factor) of CMOS passive devices while ensuring stability over PVT variations. It is implemented in the form of a grounded NR circuit to support single-ended RF circuit applications. Various circuit techniques such as a diode-connected load, a proportional-to-absolutetemperature (PTAT) current source and an adaptive body-biasing based threshold voltage compensation have been adopted to obtain a stable negative resistance value. Simulation results show that the Qfactor of on-chip spiral inductors loaded by the proposed NR circuit is improved from 6 to 60 at 1 ㎓ under typical corner conditions (tt, 1.2V, 27 ℃). The simulated Q-factor variation in corner conditions is approximately 37, which is approximately 6.5 times more stable than conventional NR circuit without compensation.

A 0.8-V, 55.1-dB DR, 100 Hz Low-Pass Filter with Low-Power PTAT for Bio-Medical Applications

This paper presents a power efficient transconductor-capacitor () filter for front-end processing of bio-medical signals. A low voltage, low-power transconductor with improved output resistance is proposed. It offers a transconductance () of 5.85 nS while operating at a supply voltage () of 0.8 V. Furthermore, a low-power Proportional to Absolute Temperature (PTAT) current reference circuit is designed to bias the transconductor and to make independent of temperature. It follows PTAT characteristics in the temperature range of −20C to 70C and is less sensitive to variations. A second-order Butterworth low-pass filter (LPF) with a cutoff frequency of 100 Hz is implemented to validate the proposed transconductor and the PTAT circuit. The filter is designed in UMC 65 nm CMOS process and it takes an area of 0.065 mm. While consuming a power of 47 nW, it offers a dynamic range (DR) of 55.1 dB. Figure-of-merit (FoM) of the filter is as low as J, which is found to be on par with the filters reported in the literature.

CMOS time-mode smart temperature sensor using programmable temperature compensation devices and $$\Delta \Sigma$$ time-to-digital converter

This work presents a time-mode smart temperature sensor in a standard 180 nm CMOS process, intended for on-chip thermal monitoring applications. A new temperature-to-pulse converter (TPC) is proposed utilising programmable temperature compensation devices, where a dual delay-line configuration is adopted, namely sensor and reference delay-lines. The proportional to absolute temperature (PTAT) delay offered by the sensor delay-line has a temperature coefficient (TC) of 720 ppm/°C, whereas almost constant delay possessed by the reference delay-line has a TC of 60 ppm/°C, over 0–100 °C temperature range. The proposed 1st-order $$\Delta \Sigma$$ time-to-digital converter (TDC) serves as the smart sensor readout, where a novel delay-cell is proposed using multipath approach. The projected $$\Delta \Sigma$$ TDC achieves 30 ns full-scale range at 9 ps resolution. The dual delay-line configuration in the TPC and the dynamic element matching in the $$\Delta \Sigma$$ TDC bound the inaccuracy of the proposed smart temperature sensor to ± 0.68 °C. The sensor shows a resolution of 0.03 °C at 0.5 $$\upmu \hbox {s}$$ conversion time.

1.8 V, 25.9 nW, 91.86 dB dynamic range second‐order lowpass filter tunable in the range 4–100 Hz

A second-order lowpass Butterworth filter with tunable bandwidth capable of offering a dynamic range of 91.86 dB operating on a supply voltage of 1.8 V is presented. The proposed filter is based on a sub-threshold source follower. The transistor bias currents are switched to enable the bandwidth tuning in the range 4–100 Hz. A proportional to absolute temperature (PTAT) current reference circuit helps to keep the bandwidth intact across process, voltage and temperature variations. The filter, designed in 0.18 µm standard CMOS process, consumes 25.9 nW making it a potential candidate for portable biomedical applications.

FR-4 PCB에 구현한 저가형 24 GHz 레이다 시스템

In this study, a 24-GHz frequency modulated continuous wave(FMCW) radar system was designed on an FR-4 board to demonstrate the feasibility of low-cost radar systems. As the FR-4 substrate has a large substrate loss, its thickness was carefully determined considering line loss and radiation efficiency. Additionally, to operate the radar chip in the industrial scientific and medical(ISM) band without using a phase locked loop(PLL), we superposed and used the triangular wave signal of the DAC and proportional to absolute temperature (PTAT) voltages as a VCO tuning voltage. The designed radar has an operating frequency range of 24.02～24.25 GHz, output power of 4 dBm, a total receiver voltage gain of 66 dB, and an antenna gain of 9 dBi. The RF and MCU boards both use FR-4, and the size of the radar module is 4 cm×4.5 cm.

Resistorless Frequency Locked On-Chip Oscillator with Proportional-to-Absolute Temperature References

A 36-kHz frequency locked on-chip oscillator is proposed, the proportional-to-absolute temperature (PTAT) current and voltage generator is presented to eliminate conventional temperature-compensated resistors. The resistorless approach reduces the process variation of frequency and the chip area. The oscillator is fabricated in 0.18-[Formula: see text]m standard CMOS process with an active area of 0.072[Formula: see text]mm2. The temperature coefficient of frequency is 48[Formula: see text]ppm/∘C at best and 82.5[Formula: see text]ppm/∘C on average over [Formula: see text]–70∘C and the frequency spread is 1.43% ([Formula: see text]/[Formula: see text] without calibration. The supply voltage sensitivity is 1.8%/V in the range from 0.65[Formula: see text]V to 1[Formula: see text]V and the power consumption is 95[Formula: see text]nW under the supply voltage of 0.65[Formula: see text]V.

A 0.7-V 28-nW CMOS Subthreshold Voltage and Current Reference in One Simple Circuit

This paper presents a low-power and high-precision voltage and current reference (VCR) in one simple circuit. The voltage reference is derived from the threshold voltage difference between an I/O (i.e., 3.3-V NMOS) and standard (i.e., 1.8-V NMOS) transistors with temperature-independent bias current, and the current reference is the voltage reference divided by a temperature-insensitive resistor. The resistor is made up by series connection of a proportional-to-absolute-temperature (PTAT) NWELL resistor and a complementary-to-absolute-temperature (CTAT) high-resistance poly resistor in series. Implemented in a standard 0.18- $\mu \text{m}$ CMOS process, the proposed VCR circuit takes an active area of only 0.055 mm2. The measured voltage and current references ( $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ ) at room temperature are 368 mV and 9.77 nA, respectively. The measured average temperature coefficient (TC) of $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ are 43.1 ppm/°C and 149.8 ppm/°C over a temperature range of −40~125°C with one-time trimming and the variation coefficients are 0.35% and 1.6%, respectively. The measured voltage and current line sensitivities are 0.027%/V and 0.6%/V, respectively. The minimum supply voltage is 0.7 V with a total power consumption of 28 nW. The measured power supply ripple rejection (PSRR) of $\text{V}_{\mathrm {ref}}$ is −65 dB @DC and −39.4 dB at frequencies higher than 1 Hz.

A 763 pW 230 pJ/Conversion Fully Integrated CMOS Temperature-to-Digital Converter With +0.81 °C/−0.75 °C Inaccuracy

A sub-nW fully integrated temperature sensor is presented that digitizes temperature via a capacitive charging time feedback loop controlled by a least significant bit (LSB)-first algorithm. Specifically, an ultra-low-power current reference generator charges two metal–insulator–metal (MIM) capacitors $C_{\mathrm{ top}}$ and $C_{\mathrm{ bot}}$ , generating $V_{\mathrm{ ramp,top}}$ and $V_{\mathrm{ ramp,bot}}$ which are then compared to a constant with temperature (CWT) voltage and a proportional to absolute temperature (PTAT) voltage, respectively. Temperature is then digitized by matching the charging time between the $V_{\mathrm{ ramp,top}}$ and $V_{\mathrm{ ramp,bot}}$ via feedback tuning of $C_{\mathrm{ top}}$ driven by an energy-efficient digital processing unit (DPU) for direct ultra-low-power digital readout. The design is fabricated in 65 nm complementary metal–oxide–semiconductor, and measurement from 12 samples reveals a maximum temperature error of +1.61 °C/−1.53 °C (+0.86 °C/−0.83 °C) and +0.81 °C/−0.75 °C when operating from 0 °C to 100 °C after two-point (three-point) calibration without and with trimming, respectively. Operating from a 0.5 V supply, the 12 samples consumed an average power of 763 pW at 20 °C, which after a 0.3 s conversion time results in 230 pJ/conversion.

A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient

This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[Formula: see text]nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55[Formula: see text]V, and generates a 286[Formula: see text]mV reference voltage with a temperature coefficient of 59[Formula: see text]ppm/∘C. The circuit takes 413[Formula: see text]nA current from 0.55[Formula: see text]V supply and occupies 0.00986[Formula: see text]mm2 of active area.

A 68-nW novel CMOS sub-bandgap voltage reference circuit

This paper proposes a CMOS sub-bandgap reference (sub-BGR) circuit without resistors for ultra-low power applications. The BGR core circuit consists of a vertical PNP bipolar transistor, a temperature-compensation amplifier and a Proportional to Absolute Temperature (PTAT) voltage generator. The PTAT voltage generator consists of four p-type transistors and generates a positive temperature dependent voltage, which compensates for the negative temperature dependent base-emitter voltage in a PNP bipolar transistor. The circuit generates a sub-bandgap voltage of silicon. The sub-BGR is fabricated with 65-nm standard CMOS process with an area of 400 μm × 80 μm. Experimental results demonstrate that this sub-BGR circuit can generate a 202.8 mV reference voltage with a power consumption of 68 nW.

A CMOS temperature sensor based on duty-cycle modulation with calibration

In this paper, a digital CMOS temperature sensor based on duty-cycle modulation with digital calibration is presented. The temperature sensor generates a duty-cycle-modulated signal by applying a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current derived from substrate bipolar junction transistors (BJT) to an integrator followed by a window comparator. The duty-cycle-modulated signal is then converted to a digital representation of temperature with two counters. Calibration is performed in the digital domain with three calibration parameters. Dynamic element matching (DEM) and chopping techniques are also used to minimize the errors caused by the component mismatch. The prototype chip is fabricated in a $$0.5\,\upmu \hbox {m}$$ CMOS process. The chip area occupies $$2.3\,\hbox {mm}^2$$. Measurement results from 11 test chips show that an inaccuracy of $$-1.1{-}0.5\,^{\circ }\hbox {C}$$ is achieved over the temperature range from $$-35$$ to $$85\,^{\circ }\hbox {C}$$ after calibration. The 2.5 V supply voltage is utilized and the total power consumption is 0.83 mW at a conversion rate of 0.5 kSa/s with a resolution of $$0.0625\,^{\circ }\hbox {C/LSB}$$, leading to $$6.48-\hbox {nJ}^{\circ }\hbox {C}^2$$ resolution figure of merit (FoM) and $$2951.1-\hbox {nJ}\%^2$$ accuracy FoM.

A PVT compensated nano-ampere current reference in 0.18 µm CMOS

A PVT compensated sub-µA current reference is proposed in this paper. It is based on the summation of a proportional to absolute temperature (PTAT) current with a complementary to absolute temperature current. The current generators are realized using the subthreshold beta multipliers. The PTAT current generator of the proposed current reference behaves always as PTAT independent of transistor sizing. The process compensation technique is based on the concept of an inverse process dependency between $$\beta \left( { = \mu C_{OX} {W \mathord{\left/ {\vphantom {W L}} \right. \kern-0pt} L}} \right)$$β=μCOXW/L and the threshold voltage $$V_{TH}$$VTH of the MOS transistor at any process corner. A current reference of 100 nA is implemented in CMOS 0.18 µm technology and studied through simulation. The proposed circuit has a temperature coefficient of 335 ppm/°C in the temperature range of 0---100 °C. It provides a low process variation ofý?ý2.1% and a lower line sensitivity of 0.093%/V in the supply voltage range of 1.35---3 V. It achieves a better figure of merit of 5.487% compared to the current references reported in the literature.

A Low Voltage Bandgap Current Reference with Low Dependence on Process, Power Supply, and Temperature

The minimum power supply voltage of a typical bandgap current reference (BGCR) is limited by operating temperature and input common mode range (ICMR) of a feedback amplifier. A new BGCR using a bandgap voltage generator (BGVG) is proposed to minimize the effect of temperature, supply voltage, and process variation. The BGVG is designed with proportional to absolute temperature (PTAT) characteristic, and a feedback amplifier is designed with weak-inversion transistors for low voltage operation. It is verified with a 0.18-㎛ CMOS process with five corners for MOS transistors and three corners for BJTs. The proposed circuit is superior to other reported current references under temperature variation from -40℃ to 120℃ and power supply variation from 1.2 V to 1.8 V. The total power consumption is 126 ㎼ under the conditions that the power supply voltage is 1.2 V, the output current is 10 ㎂, and the operating temperature is 20℃.

Area-efficient all-digital pulse-shrinking smart temperature sensor with improved accuracy and resolution.

An all-digital CMOS (Complementary Metal-Oxide Semiconductor) pulse-shrinking smart temperature sensor (PSSTS) is proposed to deliver the merits of area efficiency, improved accuracy, and high resolution. First, an inverter-based temperature-sensing delay line generates a pulse with a width proportional to absolute temperature (PTAT). Then, a pulse-shrinking delay line (PSDL) with a pulse-mixing scheme (PMS) measures the PTAT pulse through pulse shrinking. The two delay lines become area efficient when the channel length of transistors is long. Conventionally, the area-efficient PSDL decreases the time resolution. Thus, the all-digital PMS considerably enhances the time resolution and achieves an excellent sensor resolution. Finally, a time subtractor improves sensor accuracy by effectively eliminating the offset error effects. The proposed sensor was implemented in a Taiwan Semiconductor Manufacturing Company 0.35-μm CMOS process and occupied an area of 0.0247 mm2, which is the best area among related studies. The PSSTS exhibited an improved inaccuracy from a maximal inaccuracy of 1.95 °C to 1.5 °C and an excellent resolution of approximately 0.05 °C/LSB. Experimental results prove that this study is area-efficient and achieves improved accuracy and high resolution.

All MOS noise-shaped time-mode temperature sensor

All MOS smart temperature sensor is presented in this work using digital-intensive temperature to time converter and noise-shaped time-to-digital converter (TDC). The temperature to time converter is designed using novel delay elements, where the output of a proportional to absolute temperature (PTAT) sensor delay line having a temperature coefficient of 2037 ppm/C∘, is compared with a reference delay line having a temperature coefficient of 80 ppm/C∘. The proposed multipath delay cell is utilized in the design of a noise-shaped TDC, which achieves 8 ps raw resolution over 25 ns dynamic range(DR). Because of quantization and mismatch noise-shaping, the simulation error of the sensor is limited to ±0.71C∘ after two-point calibration, over a temperature range from 0C∘ to 100C∘. The design achieves a resolution of 0.032C∘ at a conversion rate of 5.5 MS/s in SCL 180 nm 1.8 V/3.3 V 1P4M CMOS process.

5-Gb/s linear re-driver in 180 nm CMOS technology

A single lane, dual channel, 5-Gb/s linear re-driver has been developed and fabricated in low cost 0.18-μm CMOS technology. Some techniques have been applied to attain a very power efficient, low complexity re-driver: transistor optimization, forward scaling design, negative Miller capacitance, and inductive peaking. In addition, the re-driver achieves very good linearity thanks to careful ordering of design blocks. To combat with temperature effect and process variation, some techniques such as ratio-based design and the use of proportional to absolute temperature (PTAT) reference current have also been used. The chip only consumes approximately 90 mA in 5-Gb/s bidirectional operation from a single 1.8 V power supply.

A Study on Bandgap Reference Circuit With Leakage-Based PTAT Generation

This paper presents detailed analyses on leakage-based bandgap reference (BGR) circuit for ultralow-power applications. Design considerations for power supply rejection ratio and noise characteristics are provided with pole/zero analysis. Startup settling issue is also discussed with measurements. For verification, a test BGR circuit is implemented in a 0.18- $\mu \text{m}$ CMOS technology. The standard deviation of proportional-to-absolute-temperature (PTAT) voltages measured from 20 chips is 1.15% at 30 °C. The BGR also uses two PTAT voltages to reduce the resistance for complementary-to-absolute-temperature generation, hence alleviating the tradeoff limitation between power consumption and area cost. With an active area of 0.056 mm2, the BGR consumes 19 nW at room temperature. Measurements from 20 chips show a standard deviation of 0.54% at 30 °C without any trimming, a temperature dependence of 143 ppm/°C and a line regulation of 2.4%/V.

A 0.9-V 33.7-ppm/°C 85-nW Sub-Bandgap Voltage Reference Consisting of Subthreshold MOSFETs and Single BJT

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors and a single BJT is presented in this brief. The proposed sub-BGR consists of a novel complementary-to-absolute-temperature (CTAT) voltage generator based on a scaled emitter-base voltage of a BJT, and an improved proportional-to-absolute-temperature (PTAT) voltage generator based on stacking of $\Delta V_{\mathbf {GS}}$ of sub- $V_{\mathbf {TH}}$ MOSFETs. As the CTAT circuit achieves a reduced absolute value of the negative TC, the PTAT circuit achieves reduced power consumption without consuming a large chip area. The proposed sub-BGR circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that the sub-BGR circuit can run with a supply voltage down to 0.9 V while the power consumption is only 85 nW. An average TC of 33.7 ppm/°C and a PSRR of better than −40 dB over the full frequency range are achieved.