Proportional Absolute Temperature Research Articles

A Temperature-Robust Envelope Detector Receiving OOK-Modulated Signals for Low-Power Applications

This paper presents a passive Envelope Detector (ED) to be used for reception of OOK-modulated signals, such as in Wake-Up Receivers employed within Wireless Sensor Networks, widely used in the IoT. The main goal is implementing a temperature compensation mechanism in order to keep the passive ED input resistance roughly constant over temperature, making it a constant load for the preceding matching network and ultimately keeping the overall receiving chain sensitivity constant over temperature. The proposed ED was designed using STMicroelectronics 90 nm CMOS technology to receive 1 kbps OOK-modulated packets with a 433 MHz carrier frequency and a 0.6 V supply. The use of a block featuring a Proportional-to-Absolute Temperature (PTAT) current yields a 5 dB reduction in sensitivity temperature variation across the −40 °C to 120 °C range. Moreover, two different implementations were compared, one targeting minimal mismatch and the other one targeting minimal area. The minimal area version appears to be better in terms of estimated overall chain sensitivity at all temperatures despite a higher sensitivity spread.

A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference

—A low temperature coefficient (TC), low power subthreshold CMOS voltage reference (CVR) over a wide temperature range is presented in this paper. The proposed circuit employs the voltage difference between the two inputs of the operational amplifier as the proportional to absolute temperature (PTAT) voltage and the complementary to absolute temperature (CTAT) voltage, which is obtained by the ΔVGS of different-threshold transistors biased in the subthreshold region. The proposed CVR was designed in the 0.18-μm CMOS process with a total area of 0.0049 mm2. It achieves an average temperature coefficient (TC) of 10.3 ppm/°C over a temperature range of −40 °C–120 °C, with a TC of 4.9 ppm/°C at the TT corner. The measured power supply rejection ratio (PSRR) is −65 dB at 10 Hz and −30 dB at 1 MHz, while the power consumption is 59 nW at a supply voltage of 1 V. The average line sensitivity (LS) is 0.16 %/V, and the LS is 0.09 %/V at the TT corner.

A pseudo resistor with temperature self-adaptive scheme

A temperature self-adaptive ultra-high-resistance pseudo-resistor (PR) circuit is proposed for a wide range of biomedical applications. It acts as a relatively constant resistor over a wide temperature range (−40 °C–85 °C) due to its potential to compensate for the impact of the temperature-induced current. Hence, the performance of many biomedical analog intellectual property (IP) circuits can be effectively improved with temperature variations. The proposed circuit consists of a gate-voltage-controlled pseudo-resistor and a proportional-to- absolute-temperature (PTAT) circuit. Besides, its analysis and proof of concept with the self-adaptive scheme are presented. The circuit is designed in standard 0.18 μm CMOS technology and occupies a silicon area of 18.5 × 43.7 μm2. It consumes 12 nW with a single power supply of 1.8 V. The post-layout simulation results demonstrate that the proposed pseudo-resistor could adequately improve the temperature-induced resistance variation by up to 18X while consuming ultra-low power and providing relatively high-temperature independence compared to the prior art.

A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation

A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the ΔVGS of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.

A 2.41 ppm/°C bandgap voltage reference with second‐order curvature compensation

SummaryA current‐mode (CM) bandgap voltage reference (BGR) with second‐order curvature compensation is presented in this paper. The proposed CM BGR offers a simple compensation structure that requires only six additional transistors compared with traditional BGR designs, making it an attractive solution for low temperature coefficient (TC) voltage references. Proportional to absolute temperature (PTAT) current digital‐to‐analog converters (DACs) are used to suppress the effect of process variation and device mismatch on TC. The compensation signal is generated using the voltage difference of two bipolar junction transistor (BJT) emitter–bases whose currents are the sum and difference of the PTAT current and the zero to absolute temperature (ZTAT) current, respectively. The proposed CM BGR is designed with 0.18‐μm BIPOLAR CMOS DMOS process. A TC is 2.41 ppm/°C over a wide temperature range of −40°C to 150°C. The linear sensitivity of the supply voltage from 1.2 to 2 V is 0.027%/V. With an active area of 0.0721 mm2, it consumes 68 μA at room temperature. The integrated output noise from 0.1 to 10 Hz is 21.9 μV.

A 2.25 ppm/°C High-Order Temperature-Segmented Compensation Bandgap Reference

This paper presents a bandgap reference (BGR) with high-order temperature-segmented compensation. The compensation signal is generated using the voltage difference between two bipolar junction transistor (BJT) emitter bases, each of which individually loads a proportional-to-absolute temperature (PTAT) current and a zero-to-absolute temperature (ZTAT) current. The proposed BGR achieves a low-temperature coefficient (TC) over a wide temperature range. Simulations using the 0.18 μm Bipolar-CMOS-DMOS process show a typical TC of 2.25 ppm/°C from −40 °C to 125 °C. With an active area of 0.07986 mm2, it consumes 36 μW power under an operating voltage of 1 V. The integrated output noise from 0.1 Hz to 10 Hz is 81.1 μV.

A 10.5 ppm/°C Modified Sub-1 V Bandgap in 28 nm CMOS Technology with Only Two Operating Points

Reference voltage/current generation is essential to the Analog circuit design. There have been several ways to generate quality reference voltage using bandgap reference (BGR) and there are mainly two types: current mode and voltage mode. The current-mode bandgap reference (CBGR) is widely accepted in industry due to having an output voltage which is below 1 V. However, its drawbacks include a lack of proportional to absolute temperature (PTAT) current availability, a large silicon area, multiple operating points, and a large temperature coefficient (TC). In this paper, various operating points are explained in detail with diagrams. Similar to the conventional voltage mode bandgap reference (VBGR) circuits, modifications of the existing circuits with only two operating points have also been proposed. Moreover, the proposed BGR occupies a much smaller area due to eliminating the complimentary to absolute temperature (CTAT) current-generating resistor. A new self-biased opamp was introduced to operate from a 1.05 V supply, reducing systematic offset and TC of the BGR. The proposed solution has been implemented in 28 nm CMOS TSMC technology, and extraction simulations were performed to prove the robustness of the proposed circuit. The targeted mean BGR output is 500 mV, and across the industrial temperature range (−40 to 125 °C), the simulated TC is approximately 10.5 ppm/°C. The integrated output noise within the observable frequency band is 19.6 µV (rms). A 200-point Monte Carlo simulation displays a histogram with a 2.6 mV accuracy of 1.2% (±3-sigma). The proposed BGR circuit consumes 32.8 µW of power from a 1.05 V supply in a fast process and hot (125 °C) corner. It occupies a silicon area of 81 × 42 µm (including capacitors). This design can aim for use in biomedical and sensor applications.

MOSFET only low power sub‐bandgap voltage reference by subtraction of slope compensated proportional‐to‐absolute‐temperature voltage references

SummaryVoltage references are typically designed by combining a complimentary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltage references. However, in contrast to conventional voltage references, the proposed circuit generates a voltage reference by subtracting two PTAT voltages, resulting in an extremely low process‐dependent voltage reference. A novel subtractor is also proposed for subtracting PTAT voltages, which is used to generate the reference voltage. The temperature coefficient of the proposed voltage reference is further improved using a novel PTAT slope compensation technique. The proposed voltage reference is a MOS‐only ultra‐low power circuit that works with sub‐bandgap supply voltage. Simulation results using UMC 0.18 m technology MOSFETs show that the proposed circuit has a line sensitivity of 0.5%/V, a temperature coefficient of 21.37 ppm/° C, a power consumption of 15.6 nW, and an output voltage variation of only 0.22% due to process variations.

A High-Precision Current-Mode Bandgap Reference With Low-Frequency Noise/Offset Elimination

This brief presents a low-noise, low-offset bandgap reference for the biomedical electronic systems application. In order to reduce the low-frequency noise and increase the accuracy, the low-frequency noise/offset elimination technique based on current-mode bandgap reference (BGR) is proposed. Besides, this BGR utilizes a proportional to absolute temperature (PTAT) resistor feedback technique to minimize the low-frequency noise and offset from the current mirror. The proposed BGR is implemented in a 180 nm deep n-well CMOS process occupying an active area of 0.0725 mm2. The measured results indicate that the BGR outputs 0.6 V voltage and consumes 69 μA current under 1.2 V supply voltage. It can achieve 3.5 μV(rms) noise from 0.1 to 10 Hz and a 0.21% DC accuracy.

A Hybrid Magnetic Current Sensor With a Multiplexed Ripple-Reduction Loop

This article presents a hybrid magnetic current sensor for galvanically isolated measurements. It consists of a CMOS chip that senses the magnetic field generated by current flowing through a lead-frame-based current rail. Hall plates and coils are used to sense low-frequency (dc to 10 kHz) and high-frequency (10 kHz to 5 MHz) magnetic fields, respectively. With the help of on-chip calibration coils, the biasing current of the Hall plates is trimmed to match the sensitivity of the Hall and coil signal paths. The sensitivity drift of the coil path with temperature is compensated by using temperature-dependent gain-setting resistors, while the drift of the Hall path is compensated by biasing the Hall plates with a proportional-to-absolute-temperature (PTAT) current. The resulting sensitivity drift is less than 9% from –40 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C to 80 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C. The offset of the Hall plates is reduced by the current spinning technique, and the resulting ripple is suppressed by a multiplexed ripple-reduction loop (MMRL). Fabricated in a standard 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m CMOS process, the current sensor occupies 4.6 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and draws 7.8 mA from a 1.8-V supply. It achieves a gain variation of only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 2% in a 5-MHz BW. It also achieves high energy efficiency, with an figure of merit (FoM) of 1.6 fW/Hz.

A 6.435-nW, 26.2-ppm/°C hybrid bandgap reference with stacked ΔVGS compensation in sub-threshold region

This paper illustrates a methodology to design an ultra-low power hybrid bandgap reference (HBR) with high accuracy to counteract the effect of temperature using single BJT and MOSFETs working in subthreshold region. Based on compensated VBE and ΔVth, the study provides a new insight into compensation of complementary-to-absolute-temperature (CTAT) voltage with a nano-watt proportional-to-absolute-temperature (PTAT) voltage generator with reduced threshold voltage-induced process variation. Designed in a 180 nm CMOS process, the circuit has a measured temperature coefficient of 26.2 ppm/°C with a wide temperature range of −40 °C∼125 °C and an overall variation coefficient of 0.234% among 9 chips with an active area of 0.0264 mm2. The experimental result shows that the proposed HBR circuit can operate with a supply voltage down to 1.1 V and a full frequency PSRR of better than −35 dB while the power consumption is only 6.435 nW.

Room-Temperature CMOS Monolithic Resonant Triple-Band Terahertz Thermal Detector

Multiband terahertz (THz) detectors show great application potential in imaging, spectroscopy, and sensing fields. Thermal detectors have become a promising choice because they could sense THz radiations on the whole spectrum. This paper demonstrates the operation principle, module designs with in-depth theoretical analysis, and experimental validation of a room-temperature CMOS monolithic resonant triple-band THz thermal detector. The detector, which consists of a compact triple-band octagonal ring antenna and a sensitive proportional to absolute temperature (PTAT) sensor, has virtues of room-temperature operation, low cost, easy integration, and mass production. Good experimental results are obtained at 0.91 THz, 2.58 THz, and 4.2 THz with maximum responsivities of 32.6 V/W, 43.2 V/W, and 40 V/W, respectively, as well as NEPs of 1.28 μW/Hz0.5, 2.19 μW/Hz0.5, and 2.37 μW/Hz0.5, respectively, providing great potential for multiband THz sensing and imaging systems.

A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications

A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators compensate for the approximated proportional to absolute temperature (PTAT) delay arising from the leakage currents in the switches. This relaxation oscillator is designed to output a square wave with a frequency of 64 kHz in a duty cycle of 50% at a 1.1 V supply. The simulation results demonstrated that the circuit can generate a square wave, with stable frequency, against temperature and supply variation, while exhibiting low current consumption. For the temperature range from −20 °C to 80 °C at a 1.1 V supply, the oscillator’ output frequency achieved a temperature coefficient (T.C.) of 12.4 ppm/°C in a typical corner in one sample simulation. For a 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corners and room temperatures, the simulated line sensitivity is 0.045%/V with the supply from 1.1 V to 1.6 V, and the dynamic current consumption is 552 nA. A better figure-of-merit (FoM), which equals 0.129%, is displayed when compared to the representative prior-art works.

Temperature-Insensitive Ka-Band Transceiver With Ultralow-Noise Self-Calibrated Low Dropout Regulator in 65-nm CMOS

This article proposes a Ka-band transceiver with an integrated local oscillator (LO) generator and multiple low dropout regulators (LDOs) to eliminate the strict requirements to the external power supply network. The proposed self-calibrated LDO eliminates the use of a bandgap reference circuit and its large flicker noise contribution in traditional power regulators to achieve ultralow-noise performance. The output of the proposed LDO is self-calibrated with temperature and process variations by autoconfiguring the feedback coefficient through a digital loop to guarantee the stable performance of its loaded high-speed circuits. The stable gain and output power of the transceiver with temperature variation are achieved by on-chip multiple self-compensation schemes, which include a self-sensing LDO for the power amplifier, a constant- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{\!m}$ </tex-math></inline-formula> bias circuit for the amplification stages, and the temperature-compensated intermediate-frequency amplifiers (TC IFAs) with proportional-to-absolute-temperature (PTAT) gain to further compensate for the gain deviation caused by the second-order effect and large-signal performance difference. Implemented in 65-nm CMOS technology, measurements indicate that the output noise of the proposed LDO is as low as 15 nV/sqrt (Hz) at 10-kHz offset and the integrated power network greatly reduces the noise influence on the LO signal compared with the traditional bandgap-referenced LDO. Furthermore, due to the adoption of the proposed temperature compensation scheme, the small-signal gains of the receiver and transmitter only fluctuate by 1.1 and 1.3 dB from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40\,\,^{\circ }\text{C}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$85~^{\circ }\text{C}$ </tex-math></inline-formula> , respectively, and the output saturated power of the transmitter varies by 0.7 dBm over the entire temperature range.

MOS only nano-watt sub-bandgap voltage reference

This paper presents a nano-watt bandgap voltage reference (BGR). The self-cascode structure is provided as a proportional-to-absolute-temperature (PTAT) voltage. Due to the low slope of the PTAT voltage, a voltage divider consisting of five similar MOSFET transistors is presented. The resulting output voltage will be one-fifth of the complementary-to-absolute-temperature voltage and four-fifths of the PTAT voltage. All MOSFETs are standard CMOS transistors biased in the sub-threshold region where one of them is utilized as a diode. Post-layout simulation results using the standard 0.18 µm CMOS process show a nominal output voltage of 0.132 V. The power consumption is 12.7 nW at 0.7 V of the power supply. The average temperature coefficient (TC) is about 28.5 ppm/°C over a temperature range of 0 °C–100 °C. The proposed BGR occupies a small area of 0.00083 mm2.

An all-digital CMOS temperature sensor with a wide supply voltage range

This paper proposes a MOSFET-based all-digital temperature sensor fabricated in a standard 55-nm CMOS process. The temperature sensing elements of the sensor are composed of ring oscillators, which convert temperature information into frequency information. The frequency ratio’s proportional to absolute temperature (PTAT) feature is generated by using two separate frequency oscillators with varied temperature sensitivity. The frequency-to-digital converter (FDC) converts frequency information into digital representation without introducing any overhead reference clock. A die area of 1915µm2 is occupied, owing to the all-digital architecture. After two-point calibration, the proposed sensor achieves an error of -0.4°C∼+0.6°C throughout a temperature range of -40°C∼125°C. With the help of class-adjustable oscillators, the sensor can function in a wide supply voltage range from 0.5V to 1.2V. It obtains a resolution of 0.166°C at room temperature with a dissipation of 2.5µW.

High-performance sub-1 V CMOS voltage reference with low supply voltage

A CMOS voltage reference with low line sensitivity, high PSRR, and low supply voltage is presented. Usually, CMOS voltage references use proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) behaviours to generate temperature-compensated reference voltages. Since the PTAT-behaviour-generator circuit requires more transistors with complex circuitry than the CTAT-behaviour-generator circuit, these voltage references require a large number of transistors. Therefore, this technique does not offer much improvement in the circuit's complexity, power consumption, and area. To overcome these drawbacks, some of the researchers have presented voltage references based on the subtraction of two CTAT behaviours but they have used two different circuits for CTAT voltages/currents. In contrast, only one standard beta-multiplier circuit is used in the proposed design to generate CTAT voltages which further decreases circuit complexity and area. Also, operational amplifiers have been employed in the negative feedback loop to achieve low line sensitivity and high PSRR. The proposed circuit offers an output reference voltage of 350 mV with a temperature coefficient of 31.5 ppm/°C for the temperature varying from −55 °C to 125 °C. The line sensitivity and PSRR are observed as 0.015 %/V (for supply voltage ranging from 0.65 V to 3.5 V) and −85.4 dB (for the frequency of 100 Hz), respectively.

Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing

Smart material implication (SIMPLY) logic has been recently proposed for the design of energy-efficient Logic-in-Memory (LIM) architectures based on non-volatile resistive memory devices. The SIMPLY logic is enabled by adding a comparator to the conventional IMPLY scheme. This allows performing a preliminary READ operation and hence the SET operation only in the case it is actually required. This work explores the SIMPLY logic scheme using nanoscale spin-transfer torque magnetic tunnel junction (STT-MTJ) devices. The performance of the STT-MTJ based SIMPLY architecture is analyzed by varying the load resistor and applied voltages to implement both READ and SET operations, while also investigating the effect of temperature on circuit operation. Obtained results show an existing tradeoff between error rate and energy consumption, which can be effectively managed by properly setting the values of load resistor and applied voltages. In addition, our analysis proves that tracking the temperature dependence of the MTJ properties through a proportional to absolute temperature (PTAT) reference voltage at the input of the comparator is beneficial to mitigate the reliability degradation under temperature variations.

A Low-temperature-coefficient Bandgap Voltage Reference for Sar Adc

Abstract The paper verifies a curvature-compensated bandgap reference circuit, which generates 1.2V bandgap voltage. Bandgap voltage comprises two parts: proportional to absolute temperature (PTAT) voltage from the bandgap core and complementary to absolute temperature (CTAT) voltage from the p-n junction. Simulation results across corners show that the temperature coefficient of this architecture can be less than 3ppm/°C by using the current compensation. Test results prove that the temperature coefficient achieves 5ppm/°C. The proposed bandgap consumes a power of 2mW and occupies an area of 0.15mm2 in the 0.18μm CMOS process.

Temperature compensated ring oscillator based VCO

Frequency drift due to temperature variations is a crucial design consideration and cannot always be compensated by a phase-locked loop especially when low-gain, multiband oscillators are employed. A ring oscillator architecture with reduced frequency drift over temperature is presented in this paper. The oscillator is incorporated in a phase locked loop (PLL) to produce a stable clock within the required frequency range under process, voltage, and temperature variations. The output frequency of the oscillator is compensated through a proportional to absolute temperature (PTAT) current in order to eliminate the frequency drift. A proof-of-concept PLL has been designed and fabricated in a 180 nm CMOS technology operating with 3.3 V supply voltage and providing a 480 MHz frequency. Measurement results of the fabricated chip show a frequency variation of the VCO from −1.5 % to + 0.4 % from the center frequency across the temperature range from −40 °C to 120 °C meeting the requirements for most consumer market applications. The duty cycle distortion is less than 1% across the temperature range. The phase noise of the oscillator was measured at −107 dBc/Hz.