Properties Of Transistors Research Articles

Temperature-Dependent Carrier Transport in GaN Nanowire Wrap-Gate Transistor.

For the creation of next-generation nanoscale devices, it is crucial to comprehend the carrier transport mechanisms in nanowires. Here, we examine how temperature affects the properties of GaN nanowire wrap-gate transistors (WGTs), which are made via a top-down technique. The predicted conductance in this transistor remains essentially unaltered up to a temperature of 240 K and then increases after that as the temperature rises. This is true for increasing temperature at gate voltages less than threshold voltage (Vgs < Vth). Sharp fluctuations happen when the temperature rises with a gate voltage of Vth < Vgs < VFB. The conductance steadily decreases with increasing temperature after increasing the gate bias to Vgs > VFB. These phenomena are possibly attributed to phonon and impurity scattering processes occurring on the surface or core of GaN nanowires.

Intrinsic Electronic Properties of BN-Encapsulated, van der Waals Contacted MoSe2 Field-Effect Transistors

Two-dimensional (2D) semiconductors have attracted considerable interest for their unique physical properties. Here, we report the intrinsic cryogenic electronic transport properties in few-layer MoSe2 field-effect transistors (FETs) that are fully encapsulated in ultraclean hexagonal boron nitride dielectrics and are simultaneously van der Waals contacted with gold electrodes. The FETs exhibit electronically favorable channel/dielectric interfaces with low densities of interfacial traps (< 1010 cm−2), which lead to outstanding device characteristics at room temperature, including near-Boltzmann-limit subthreshold swings (65 mV/dec), high carrier mobilities (53–68 cm2⋅V−1⋅s−1), and negligible scanning hystereses (< 15 mV). The dependence of various contact-related parameters with temperature and carrier density is also systematically characterized to understand the van der Waals contacts between gold and MoSe2. The results provide insightful information about the device physics in van der Waals contacted and encapsulated 2D FETs.

Enhancement of electrical properties of a-IGZO thin film transistor by low temperature (150 °C) microwave annealing for flexible electronics

A relatively low-temperature process is required to fabricate amorphous oxide thin film transistor (TFT) display backplanes for flexible electronics. However, in order to ensure the outstanding electrical property of TFT, a typical post-annealing process should be performed at 300 °C or above. This is not compatible with flexible substrates in the process. In our work, we applied microwave annealing (MWA) at a low-temperature (150 °C) to the oxide TFT and verified its feasibility through the evaluation of various electrical properties. Even an a-IGZO TFT by MWA at such a low-temperature shows high mobility (29.0 cm2/V s) by DC ID-VG measurement, which is 4 ∼ 5 times higher than other counterparts, indicating that the MWA process is very effective to minimize the defects in an oxide semiconductor channel. To further investigate the intrinsic mobility of TFT with negligible charge trapping, we carried out fast and pulse ID-VG measurement methods. The intrinsic mobility extracted from this measurement is found to be 35.3 cm2/V s, 21.7% higher than that of DC ID-VG. We are expecting that the low-temperature MWA process would be widely used for the process of oxide TFT in a flexible platform.

Transistor Properties of Charge-Transfer Complexes─Combined Requirements from Energy Levels and Orbital Symmetry

Tetracyanoquinodimethane (TCNQ) complexes of fluorene, dibenzofuran, dibenzothiophene, terphenyl, dithienothiophene, and carbazole show n-channel transistor properties, whereas that of diaminoterphenyl and phenothiazine exhibits ambipolar characteristics. Ambipolar transport is observed when the highest occupied molecular orbital (HOMO) level of the donor–acceptor complex is located above the ordinary hole transport limit. Since the HOMO of the charge-transfer complex is deeper than that of the component donor owing to the charge-transfer interaction, not all hole-transporting materials show hole transport in the charge-transfer complexes. In addition, the effective (super-exchange) transfer integrals have to be sufficiently large; this is frequently not satisfied when the donor HOMO is practically orthogonal to the acceptor’s lowest unoccupied molecular orbital (LUMO). By applying these criteria to calculations starting from the crystal structures, transistor properties of mixed stack charge-transfer complexes are explained.

Analysis of Multiple Fin-type Vertical GaN Power Transistors based on Bulk GaN Substrates

In this study, the multiple fin-type vertical GaN power transistor based on the GaN-on-GaN were analyzed using the two-dimensional technical computer-aided design (2-D TCAD) simulations. In the field of the electric vehicle systems requiring a high operation voltage of 1,000 V or more, the power devices have a large device area because of the long distance between the gate region and the drain region. This problem can be addressed by using the fin-type vertical GaN power transistor, which can reduce the device area due to its vertical channel. For the high current performance, the multiple fin-type structure was required. Thus, we investigated characteristics depending on the number of fin (NSUBfin/SUB). By comparing the on-state drain currents (ISUBon/SUB), the breakdown voltages (BV), and the on-resistances (RSUBon/SUB) with different NSUBfin/SUB, this study provides an understanding of the electrical properties of the multiple fin-type vertical GaN power transistor affected by NSUBfin/SUB.

Long-Term Stability in Electronic Properties of Textile Organic Electrochemical Transistors for Integrated Applications

Organic electrochemical transistors (OECTs) have demonstrated themselves to be an efficient interface between living environments and electronic devices in bioelectronic applications. The peculiar properties of conductive polymers allow new performances that overcome the limits of conventional inorganic biosensors, exploiting the high biocompatibility coupled to the ionic interaction. Moreover, the combination with biocompatible and flexible substrates, such as textile fibers, improves the interaction with living cells and allows specific new applications in the biological environment, including real-time analysis of plants' sap or human sweat monitoring. In these applications, a crucial issue is the lifetime of the sensor device. The durability, long-term stability, and sensitivity of OECTs were studied for two different textile functionalized fiber preparation processes: (i) adding ethylene glycol to the polymer solution, and (ii) using sulfuric acid as a post-treatment. Performance degradation was studied by analyzing the main electronic parameters of a significant number of sensors for a period of 30 days. RGB optical analysis were performed before and after the treatment of the devices. This study shows that device degradation occurs at voltages higher than 0.5 V. The sensors obtained with the sulfuric acid approach exhibit the most stable performances over time.

A synaptic device based on the optoelectronic properties of ZnO thin film transistors

A synaptic device based on the optoelectronic properties of ZnO thin film transistors

Optimization of 14 nm double gate Bi-GFET for lower leakage current

In recent years, breakthroughs in electronics technology have resulted in upgrades in the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy contenders due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene FET with a high-k/metal gate is proposed, which is composed of hafnium dioxide (HfO 2 ) and tungsten silicide (WSi x ) respectively . It is simulated and modelled using silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools, as well as the Taguchi L9 orthogonal array (OA). The threshold voltage (V TH ) adjustment implant dose, V TH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters. While the V TH adjustment tilt angle and the S/D implant tilt angle have both been investigated as noise factors. When compared to the initial findings before optimization, the I OFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an I OFF of 28.564 nA/µm, which is closer to the international technology roadmap semiconductor (ITRS) 2013 target than before.

Low-Temperature Direct Growth of Amorphous Boron Nitride Films for High-Performance Nanoelectronic Device Applications.

We successfully demonstrated the improvement and stabilization of the electrical properties of a graphene field effect transistor by fabricating a sandwiched amorphous boron nitride (a-BN)/graphene (Gr)/a-BN using a directly grown a-BN film. The a-BN film was grown via low-pressure chemical vapor deposition (LPCVD) at a low growth temperature of 250 °C and applied as a protection layer in the sandwiched structure. Both structural and chemical states of the as-grown a-BN were verified by various spectroscopic and microscopic analyses. We analyzed the Raman spectra of Gr/SiO2 and a-BN/Gr/a-BN structures to determine the stability of the device under exposure to ambient air. Following exposure, the intensity of the 2D/G-peak ratio of Gr/SiO2 decreased and the position of the G and 2D peaks red-shifted due to the degradation of graphene. In contrast, the peak position of encapsulated graphene is almost unchanged. We also confirmed that the mobility of a-BN/Gr/a-BN structure is 17,941 cm2/Vs. This synthetic strategy could provide a facile way to synthesize uniform a-BN film for encapsulating various van der Waals materials, which is beneficial for future applications in nanoelectronics.

Ultrasensitive Strain Sensor Based on a Tunnel Junction with an AlN/GaN Core-Shell Nanowire

Piezotronic transistor operating in the quantum tunneling regime has recently roused wide interest for developing ultrasensitive strain sensing with applications in wearable electronics and human-machine interfaces. However, the lack of a strict theoretical demonstration from a quantum perspective renders the development of such an emerging area particularly slow due to their complex fabrication process and vulnerable experimental interference. Here, by combining third-dimensional self-consistent calculation with a nonequilibrium Green's function framework, we study the intrinsic device properties of piezotronic tunneling transistor (PTT) based on $\mathrm{Al}\mathrm{N}/\mathrm{Ga}\mathrm{N}$ core-shell nanowire. The results show that strain-induced piezoelectric polarization can remarkably tune tunneling barrier height and width, both of which are increased by tensile strain and decreased by compressive strain. At a moderate strain amplitude of 1.0% and bias of 2.0 V, the strain-induced change in effective barrier height and width can reach as high as 0.5 eV and 4.0 nm, respectively. This remarkable tunability in the barrier allows for an ultrahigh on/off current ratio ${10}^{17}$, and giant gauge factor 1.2 \ifmmode\times\else\texttimes\fi{} ${10}^{8}$ in current and 1.1 \ifmmode\times\else\texttimes\fi{} ${10}^{13}$ in resistance. The performance can be further optimized by properly tailoring device architectures, including insulator thickness, nanowire length, or core-shell size. Our demonstration of the PTT with combined quantum tunneling and piezotronic effect opens a window for designing highly sensitive, large on/off ratio and low-power strain sensing.

Comparison of power transistors for WPT power inverter 44kW

This article deals with the selection of components suitable for the construction of a power voltage converter for wireless power transmission systems with a power of 44 kW, in accordance with the requirements that need to be met. At the beginning, the article highlights the properties of SiC-based power transistors. The comparison is based on the evaluation of the properties of the transistors in terms of robustness and dependability, conduction and switching losses, the driver's complexity, dimensions and price. The article deals with the simulation evaluation of power switching elements based on SiC. The comparison is made through thermal models of transistors in a Plecs environment. Features, advantages, disadvantages of power modules and discrete components are discussed.

Sensing property of Ga2O3-based extended-gate field-effect transistors for a living cell viability sensor

Sensing property of Ga2O3-based extended-gate field-effect transistors for a living cell viability sensor

Polarization-tunable interfacial properties in monolayer-MoS2 transistors integrated with ferroelectric BiAlO3(0001) polar surfaces.

With the explosion of data-centric applications, new in-memory computing technologies, based on nonvolatile memory devices, have become competitive due to their merged logic-memory functionalities. Herein, employing first-principles quantum transport simulation, we theoretically investigate for the first time the electronic and contact properties of two types of monolayer (ML)-MoS2 ferroelectric field-effect transistors (FeFETs) integrated with ferroelectric BiAlO3(0001) (BAO(0001)) polar surfaces. Our study finds that the interfacial properties of the investigated partial FeFET devices are highly tunable by switching the electric polarization of the ferroelectric BAO(0001) dielectric. Specifically, the transition from quasi-Ohmic to the Schottky contact, as well as opposite contact polarity of respective n-type and p-type Schottky contact under two polarization states can be obtained, suggesting their superior performance metrics in terms of nonvolatile information storage. In addition, due to the feature of (quasi-)Ohmic contact in some polarization states, the explored FeFET devices, even when operating in the regular field-effect transistor (FET) mode, can be extremely significant in realizing a desirable low threshold voltage and interfacial contact resistance. In conjunction with the formed van der Waals (vdW) interfaces in ML-MoS2/ferroelectric systems with an interlayer, the proposed FeFETs are expected to provide excellent device performance with regard to cycling endurance and memory density.

Impact of high-k metal oxide as gate dielectric on the certain electrical properties of silicon nanowire field-effect transistors: A simulation study

Standard Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are gaining prominence in low-power nanoscale applications. This is largely attributed to their proximity to physical and thermal limits, rendering them a compelling option for energy-efficient electronic devices. In this study, we hypothesized that the high-? HfO2 in a quasi-ballistic SiNW MOSFET acts as the gate dielectric. In this case, the data from the TCAD simulation and the model demonstrated exceptional agreement. The proposed model for a SiNW MOSFET with high-? HfO2 exhibits a consistently increasing drain current, albeit with a smaller magnitude compared to a quasi-ballistic device (QBD). Additionally, it shows reduced mobility and decreased transconductance when considering the combined effects of scattering and temperature. As gate voltage increases, temperatureinduced transconductance decline in SiNW MOSFETs becomes significant. Our method is suitable for modeling scattered SiNW MOSFETs with temperature effects, as TGF values are similar in the subthreshold region for both Near Ballistic and Scattered SiNW MOSFET models.

Effect of biaxial misfit strain on properties of ferroelectric double gate negative capacitance transistors

In order to continue Moore’s law, the reduction of power consumption has received much attention. It is necessary to develop steep devices that can overcome the “Boltzmann tyranny” and solve the problem of high power consumption of integrated circuits. Negative capacitance field-effect transistors are one of the most promising candidates in numerous steep devices. Strain engineering has been widely studied as an effective means of regulating the properties of ferroelectric thin films. However, the influence of strain on the performance of negative capacitance field-effect transistor has not been clear so far. Therefore, in this work, an analytical model of double gate negative capacitance field-effect transistor (DG-NCFET) regulated by biaxial misfit strain is proposed. Using this model, we investigate the influences of ferroelectric layer thickness and biaxial misfit strain on electrical properties of PbZr&lt;sub&gt;0.5&lt;/sub&gt;Ti&lt;sub&gt;0.5&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; (PZT)-based and CuInP&lt;sub&gt;2&lt;/sub&gt;S&lt;sub&gt;6&lt;/sub&gt; (CIPS)-based negative capacitance field-effect transistors (NCFETs), respectively. The results show that for the negative capacitance field-effect transistor based on PbZr&lt;sub&gt;0.5&lt;/sub&gt;Ti&lt;sub&gt;0.5&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;, when the ferroelectric layer thickness is increased or the compression strain is applied, the subthreshold swing and conduction current are improved, but the tensile strain has the opposite effect. For the negative capacitance field-effect transistor based on CuInP&lt;sub&gt;2&lt;/sub&gt;S&lt;sub&gt;6&lt;/sub&gt;, its performance is improved when the thickness of the ferroelectric layer is increased or the tensile strain is applied, but the device lags behind under the compressive strain. It is found that the CIPS-based NCFET exhibits better performance than PZT-based NCFET at low gate voltages.

Manipulation of the electrical and memory properties of MoS2 field-effect transistors by highly charged ion irradiation.

Field-effect transistors based on molybdenum disulfide (MoS2) exhibit a hysteresis in their transfer characteristics, which can be utilized to realize 2D memory devices. This hysteresis has been attributed to charge trapping due to adsorbates, or defects either in the MoS2 lattice or in the underlying substrate. We fabricated MoS2 field-effect transistors on SiO2/Si substrates, irradiated these devices with Xe30+ ions at a kinetic energy of 180 keV to deliberately introduce defects and studied the resulting changes of their electrical and hysteretic properties. We find clear influences of the irradiation: while the charge carrier mobility decreases linearly with increasing ion fluence (up to only 20% of its initial value) the conductivity actually increases again after an initial drop of around two orders of magnitude. We also find a significantly reduced n-doping (≈1012 cm-2) and a well-developed hysteresis after the irradiation. The hysteresis height increases with increasing ion fluence and enables us to characterize the irradiated MoS2 field-effect transistor as a memory device with remarkably longer relaxation times (≈ minutes) compared to previous works.

Surface band bending caused by native oxides on solution-processed twinned InSb nanowires with p-type conductivity.

Indium antimonide nanowires (InSb NWs) are attractive building-block candidates for bottom-up construction of high-efficiency electronics and optoelectronics due to their narrow direct band gap, fast room temperature carrier mobilities and small exciton binding energy. However, InSb NWs synthesized by the vapor-liquid-solution (VLS) mechanism generally suffer from an increased carrier and phonon scattering rate, which is thought to be caused by randomly distributed crystal defects along the NW growth direction. In this study, by utilizing the recently developed low-temperature, solution-processed technique, these crystal defects were successfully suppressed by periodically distributed twin planes to form twinned InSb nanowires. Importantly, measurements of the electrical transport properties of field effect transistors (FETs) reveal that the InSb NWs exhibit a hole-dominated conductivity with room temperature mobilities of up to 50.71 cm2 V-1 s-1, which is distinctly contrary to the intrinsic n-type InSb NWs. This observation of n-p switching behavior is probably attributed to the surface band bending effect with regard to the Fermi energy level, which is caused by surface oxide trap states arising from the native-oxide layer at the surface of the InSb NWs. All these results illustrate that the as-prepared colloidal InSb NWs can potentially be used as p-type materials for integration with next-generation nanoscale electronics and optoelectronics via surface engineering.

Epitaxial van der Waals contacts of 2D TaSe2-WSe2 metal-semiconductor heterostructures.

The electronic contact between two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors and metal electrodes is a formidable challenge due to the undesired Schottky barrier, which severely limits the electrical performance of TMD devices and impedes the exploration of their unconventional physical properties and potential electronic applications. In this study, we report a two-step chemical vapor deposition (CVD) growth of 2D TaSe2-WSe2 metal-semiconductor heterostructures. Raman mapping confirms the precise spatial modulation of the as-grown 2D TaSe2-WSe2 heterostructures. Transmission electron microscopy (TEM) characterization reveals that this two-step method provides a high-quality and clean interface of the 2D TaSe2-WSe2 heterostructures. Meanwhile, the upper 1T-TaSe2 is formed heteroepitaxially on/around the pre-synthesized 2H-WSe2 monolayers, exhibiting an epitaxial relationship of (20-20)TaSe2//(20-20)WSe2 and [0001]TaSe2//[0001]WSe2. Furthermore, characterization studies using a Kelvin probe force microscope (KPFM) and electrical transport measurements present compelling evidence that the 2D metal-semiconductor heterostructures under investigation can improve the performance of electrical devices. These results bear substantial significance in augmenting the properties of field-effect transistors (FETs), leading to notable improvements in FET mobility and on/off ratio. Our study not only broadens the horizons of direct growth of high-quality 2D metal-semiconductor heterostructures but also sheds light on potential applications in future high-performance integrated circuits.

Investigation to the Carrier Transport Properties in Heterojunction-Channel Amorphous Oxides Thin-Film Transistors Using Dual-Gate Bias

The carrier transport properties in amorphous oxide semiconductor (AOS) heterojunction thin-film transistors (TFTs) are investigated by using dual gates to control the channel of bilayer AOSs. The mobility of such heterojunction channel exhibited distinct dependences on top-gate (TG) voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text {TG}}$ </tex-math></inline-formula> ) and bottom-gate (BG) voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text {BG}}$ </tex-math></inline-formula> ) The mobility was well maintained in TG mode, where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text {TG}}$ </tex-math></inline-formula> was in line with the build-in electric field of the electron potential well (PW) formed at the heterojunction interface. In contrast, an increased <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text {BG}}$ </tex-math></inline-formula> gradually reduced the high mobility to the level of a single layer channel, since a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text {BG}}$ </tex-math></inline-formula> in the opposite direction of PW could eliminate the PW. This experimentally clarifies that the high-mobility transport path of AOS heterojunction channel locates in the interface PW and its operation demands a proper gate field direction. This were directly consolidated by the disclosed unique capacitance-voltage characteristics.

Improved Electrical Properties of EHD Jet-Patterned MoS2 Thin-Film Transistors with Printed Ag Electrodes on a High-k Dielectric.

Electrohydrodynamic (EHD) jet printing is known as a versatile method to print a wide viscosity range of materials that are impossible to print by conventional inkjet printing. Hence, with the understanding of the benefits of EHD jet printing, solution-based MoS2 and a high-viscosity Ag paste were EHD jet-printed for electronic applications in this work. In particular, printed MoS2 TFTs with a patterned Ag source and drain were successfully fabricated with low-k silica (SiO2) and high-k alumina (Al2O3) gate dielectrics, respectively. Eventually, the devices based on Al2O3 exhibited much better electrical properties compared to the ones based on SiO2. Interestingly, an improvement of around one order of magnitude in hysteresis was achieved for devices after changing the gate insulator from SiO2 to Al2O3. In effect, the results of this work for the printed MoS2 and the printed Ag source and drains for TFTs demonstrate a new approach for jet printing in the fabrication of electronic devices.