Properties Of Thin-film Transistors Research Articles

Effect of surface treated amorphous Si–Zn–Sn–O on the electrical properties of thin film transistors by Ar plasma treatment

Effect of surface treated amorphous Si–Zn–Sn–O on the electrical properties of thin film transistors by Ar plasma treatment

Specific contact resistivity reduction in amorphous IGZO thin-film transistors through a TiN/IGTO heterogeneous interlayer

Oxide semiconductors have gained significant attention in electronic device industry due to their high potential for emerging thin-film transistor (TFT) applications. However, electrical contact properties such as specific contact resistivity (ρC) and width-normalized contact resistance (RCW) are significantly inferior in oxide TFTs compared to conventional silicon metal oxide semiconductor field-effect transistors. In this study, a multi-stack interlayer (IL) consisting of titanium nitride (TiN) and indium-gallium-tin-oxide (IGTO) is inserted between source/drain electrodes and amorphous indium-gallium-zinc-oxide (IGZO). The TiN is introduced to increase conductivity of the underlying layer, while IGTO acts as an n+-layer. Our findings reveal IGTO thickness (tIGTO)-dependent electrical contact properties of IGZO TFT, where ρC and RCW decrease as tIGTO increases to 8 nm. However, at tIGTO > 8 nm, they increase mainly due to IGTO crystallization-induced contact interface aggravation. Consequently, the IGZO TFTs with a TiN/IGTO (3/8 nm) IL reveal the lowest ρC and RCW of 9.0 × 10−6 Ω·cm2 and 0.7 Ω·cm, significantly lower than 8.0 × 10−4 Ω·cm2 and 6.9 Ω·cm in the TFTs without the IL, respectively. This improved electrical contact properties increases field-effect mobility from 39.9 to 45.0 cm2/Vs. This study demonstrates the effectiveness of this multi-stack IL approach in oxide TFTs.

Boosting the performance of polymer field-effect transistors through fluorine atom substitutions and comparing the effect of various acceptor units and channel mobilities

Three conjugated copolymers, PDPP-2FTVT, PIID-2FTVT, and PNDI-2FTVT based on the 2,2′-(1E)-1,2-ethenediylbis[3-fluorothiophene] (2FTVT) core with varying acceptor units, diketopyrrolopyrrole (DPP), isoindigo (IID), and naphthalenediimide (NDI) were developed for organic field-effect transistors (OFETs). Combined electron-withdrawing fluorine atoms and vinyl linkage in the 2FTVT unit not only reduce the frontier molecular orbital energies but also extended the absorption profile and planarize the polymer backbone, manifesting synergetic effect on the strengthened molecular interactions and charge-carrier properties. The resulted copolymer, PDPP-2FTVT show highly reliable thin film transistor properties with highest hole mobility of 1.93 cm2 V−1 s−1 compared to PIID-2FTV and PNDI-2FTVT. PIID-2FTV copolymer show ambipolar characteristic with hole and electron mobilities of 0.71 and 0.03 cm2 V−1 s−1 respectively while PNDI-2FTVT exhibited the highest electron mobility of 0.20 cm2 V−1 s−1 among three copolymers. Thin film micro-structure characterization reveal that the three copolymers formed lamellar, edge-on molecular packing (for PDPP-2FTVT and PIID-2FTV), increased crystallinity with smaller π-π stacking distances, and strengthen the planarity after thermal annealing. These results contribute important progresses in solution-processed OFET and could provide a greater possibility of 2FTVT based copolymers for commercial application.

Enhancement of electrical characteristics of SnGaO thin-film transistors via argon and oxygen plasma treatment

The impact of Ar or O2 plasma treatment on the electrical characteristics of SnGaO thin film transistors (TFTs) fabricated via solution method was examined. The findings of the study revealed that Ar plasma treatment for an optimal duration enhances the electrical properties of SnGaO TFTs, including the improvement of mobility, subthreshold swing (S·S.), and on-off ratio. This result is considered to be due to the increased concentration of oxygen vacancy as donor in the channel layer. Oxygen plasma treatment has an opposite effect on the change in oxygen vacancy concentration, thereby reducing the off-state current and facilitating the adjustment of threshold voltage. However, excessive Ar or O2 plasma treatment duration led to an increase in deep defect states and a significant “hump" phenomenon in the output characteristic curve.

C-Axis Aligned Composite InZnO via Thermal Atomic Layer Deposition for 3D Nanostructured Semiconductor.

Amorphous oxide semiconductors have been widely studied for various applications, including thin-film transistors (TFTs) for display backplanes and semiconductor memories. However, the inherent instability, limited mobility, and complexity of multicomponent oxide semiconductors for achieving high aspect ratios and conformality of cation distribution remain challenging. Indium-zinc oxide (IZO), known for its high mobility, also faces obstacles in instability resulting from high carrier doping density and low ionization energy. To address these issues and attain a balance between mobility and stability, adopting a highly aligned structure such as a c-axis aligned crystalline IGZO could be advantageous. However, limited studies have reported enhanced electrical performance using crystalline IZO, likely attributed to the high thermal stability of the individual components (In2O3 and ZnO). Here, we first propose a c-axis aligned composite (CAAC) IZO with superior TFT properties, including a remarkable performance of field-effect mobility (μFE) of 55.8 cm2/(V s) and positive-bias-temperature-stress stability of +0.16 V (2 MV/cm, 60 °C, 1 h), as well as a low subthreshold swing of 0.18 V/decade and hysteresis as 0.01 V, which could be obtained through optimization of growth temperature and composition using thermal atomic layer deposition. These results surpass those of TFTs based on nanocrystalline/polycrystalline/amorphous-IZO. We conducted a thorough investigation of CAAC-IZO and revealed that the growth temperature and cation distribution profoundly influence the crystal structure and device properties. Finally, we observed excellent compositional conformality and 97% step coverage of IZO on a high-aspect-ratio (HAR) structure with an aspect ratio reaching 40:1, which is highly promising for future applications. Our results include a detailed investigation of the influence of the crystal structure of IZO on the film and TFT performance and suggest an approach for future applications.

Improvement of the electrical properties of amorphous indium-gallium-zinc oxide thin-film transistors by cross-linked CYTOP passivation

In this study, we investigated the effect of a cross-linked CYTOP passivation layer on the electrical properties of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). Cross-linked CYTOP passivation showed a deeper fluorine diffusion depth than CYTOP passivation owing to the chemical reaction between the cross-linking agent and IGZO layer. The cross-linking agent reduces the weakly bonded oxygen in the IGZO layer via a chemical reaction, enhancing fluorine diffusion into the IGZO layer. Therefore, the effect of fluorine on the IGZO layer was enhanced by using cross-linked CYTOP as a passivation layer. The diffused fluorine reduced the defect states by passivating the oxygen-related defects such as oxygen vacancies and weakly bonded oxygen and increased the carrier concentration by replacing metal–oxygen bonds with metal-fluorine bonds. IGZO TFTs with cross-linked CYTOP passivation exhibited a threshold voltage of −0.35 V, saturation mobility of 1.93 cm2/V∙s, and subthreshold swing of 0.53 V/dec. Using a cross-linked passivation layer also improved the reliability under positive gate bias stress. Consequently, a cross-linked CYTOP passivation layer can effectively improve the electrical properties of IGZO TFTs by incorporating fluorine atoms into the IGZO layer.

Improving the Electrical Properties of Zinc-Tin Oxide Thin-Film Transistors by Additive using Electrohydrodynamic Jet Technology

Oxide thin-film transistors (TFTs) are important semiconductor materials for display backplanes. To fabricate flexible displays, not only display modes but also TFTs are important. Flexible TFTs are especially needed for flexible displays, and related processes need to be developed. Printing is a good choice for the new fabrication of oxide TFTs. Electrohydrodynamic (EHD) jet printing is an excellent alternative for making flexible TFTs. To improve the electrical properties of oxide TFTs using EHD jet printing, propylene monomethyl ether acetate (PGMEA) was added to a zinc-tin oxide (ZTO) formulation. EHD jet printing was performed by Taylor cone jet mode with parameters of 2.4 kV and 0.064 µL/s to obtain uniform thin films at a substrate temperature of 50oC. Much improved TFT properties were obtained, including a mobility of 7.11 cm2/V s, on-to-off current ratio of 2.8 × 106 and subthreshold slope of 1.44 V/dec for ZTO TFT with 5 wt% of PGMEA, and a mobility of 1.43 cm2/V s, on-to-off current ratio of 2.7 × 105 and subthreshold slope of 1.32 V/dec for the ZTO TFT. Almost no hysteresis behavior was observed in the oxide TFTs with added PGMEA. We report a new way to improve the electrical properties of oxide TFTs, by the simple addition of PGMEA.

Enhancement of electrical properties of a-IGZO thin film transistor by low temperature (150 °C) microwave annealing for flexible electronics

A relatively low-temperature process is required to fabricate amorphous oxide thin film transistor (TFT) display backplanes for flexible electronics. However, in order to ensure the outstanding electrical property of TFT, a typical post-annealing process should be performed at 300 °C or above. This is not compatible with flexible substrates in the process. In our work, we applied microwave annealing (MWA) at a low-temperature (150 °C) to the oxide TFT and verified its feasibility through the evaluation of various electrical properties. Even an a-IGZO TFT by MWA at such a low-temperature shows high mobility (29.0 cm2/V s) by DC ID-VG measurement, which is 4 ∼ 5 times higher than other counterparts, indicating that the MWA process is very effective to minimize the defects in an oxide semiconductor channel. To further investigate the intrinsic mobility of TFT with negligible charge trapping, we carried out fast and pulse ID-VG measurement methods. The intrinsic mobility extracted from this measurement is found to be 35.3 cm2/V s, 21.7% higher than that of DC ID-VG. We are expecting that the low-temperature MWA process would be widely used for the process of oxide TFT in a flexible platform.

A-InGaZnO Thin-Film Transistors With Novel Atomic Layer-Deposited HfO2 Gate Insulator Using Two Types of Reactant Gases

Plasma-enhanced chemical vapor deposition is often utilized to fabricate amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with mobility of approximately 7 cm2/( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> ) using a SiOx gate insulator. For use in high-resolution organic light-emitting diode displays, this value must be markedly improved. Therefore, we used various reactants to create a HfO2 bilayer via atomic layer deposition (ALD) and examined the electrical properties of IGZO TFTs, such as their mobility and subthreshold swing (SS). By adjusting the thickness of HfO2 with H2O reactant gas, the amount of hydrogen that diffused into the IGZO channel was controlled. The IGZO TFT with a specific HfO2 bilayer gate insulator exhibited high saturation mobility of 16.75 cm2/( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> ) and an improved SS of 159 mV/dec compared to a conventional device with a HfO2 gate insulator formed using only O3 reactant gas. Furthermore, the fabricated HfO2 bilayer devices presented excellent reliability under positive bias stress and were more robust against the short-channel effect. Thus, based on the findings of this study, to improve the electrical properties of a-IGZO TFTs, the ALD process is suggested to be used to deposit a high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> gate insulator.

A Compact Amorphous In-Ga-Zn-Oxide Thin Film Transistor Pixel Circuit With Two Capacitors for Active Matrix Micro Light-Emitting Diode Displays

In this paper, we propose a novel amorphous In-Ga-Zn-oxide (a-IGZO) thin film transistor (TFT) pixel circuit for pulse width modulation (PWM) driving active matrix micro light-emitting diode (μLED) displays. The proposed pixel circuit compensates for wavelength shifts according to gray level and threshold voltage (VTH) variation of TFTs with only two capacitors. This compact operation can be achieved by simultaneous compensation for VTH along with data input in the constant current generation (CCG) circuit and the PWM circuit, which consist the pixel. Since the VTH variation in TFTs is compensated, the proposed pixel circuit can supply a uniform and stable current to the μLED throughout all gray levels. The compensation accuracy was verified by HSPICE with an oxide TFT model based on the measurement data. In addition, we analyzed the optimization method to improve the PWM driving by controlling the electrical properties of TFT, and verified this approach by simulation.

Tailored Self-Assembled Monolayer using Chemical Coupling for Indium-Gallium-Zinc Oxide Thin-Film Transistors: Multifunctional Copper Diffusion Barrier.

Controlling the contact properties of a copper (Cu) electrode is an important process for improving the performance of an amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) for high-speed applications, owing to the low resistance-capacitance product constant of Cu. One of the many challenges in Cu application to a-IGZO is inhibiting high diffusivity, which causes degradation in the performance of a-IGZO TFT by forming electron trap states. A self-assembled monolayer (SAM) can perfectly act as a Cu diffusion barrier (DB) and passivation layer that prevents moisture and oxygen, which can deteriorate the TFT on-off performance. However, traditional SAM materials have high contact resistance and low mechanical-adhesion properties. In this study, we demonstrate that tailoring the SAM using the chemical coupling method can enhance the electrical and mechanical properties of a-IGZO TFTs. The doping effects from the dipole moment of the tailored SAMs enhance the electrical properties of a-IGZO TFTs, resulting in a field-effect mobility of 13.87 cm2/V·s, an on-off ratio above 107, and a low contact resistance of 612 Ω. Because of the high electrical performance of tailored SAMs, they function as a Cu DB and a passivation layer. Moreover, a selectively tailored functional group can improve the adhesion properties between Cu and a-IGZO. These multifunctionally tailored SAMs can be a promising candidate for a very thin Cu DB in future electronic technology.

Effects of Source/Drain Electrodes on the Performance of InSnO Thin-Film Transistors.

Oxide thin-film transistors (TFTs) are of increasing interest in the field of advanced displays. In this work, we explore Al, InSnO (ITO), Ti, and Mo as source/drain electrodes of ITO TFTs. A comparison study is conducted on the electrical properties of ITO TFTs with the four categories of source/drain electrodes. Interestingly, the ITO TFT with an Al source/drain electrode exhibits better device performance, such as a field-effect mobility (μFE) of 26.45 cm2/Vs, a reasonable turn-on voltage (VON) of 2.7 V, and a steep subthreshold swing (SS) of 201.50 mV/decade. The contact properties of ITO TFTs are further analyzed, and the results show that the device with an Al electrode exhibits lower contact resistance than the other devices. However, the devices with the four electrode materials all reveal excellent stability under negative bias illumination stress (NBIS) with |ΔVTH| &lt; 1 V. This work paves the way for the practical applications of ITO TFTs in next-generation displays.

Influence of oxygen-related defects on In-Ga-Sn-O semiconductor due to plasma-enhanced atomic layer deposition of Al2O3 for low-temperature thin-film transistor in terms of electrical properties

In-Ga-Sn-O (IGTO) thin-film transistors (TFTs) were fabricated with Al2O3 gate insulators by plasma-enhanced atomic layer deposition (PEALD) at a temperature of 150 °C. Electrical performances of IGTO TFTs were significantly affected by plasma conditions when Al2O3 was deposited on IGTO thin films by PEALD. Analyses of X-ray photoemission spectroscopy revealed that excessive oxygen species activated at high plasma power above 150 W were chemisorbed to IGTO films to create excess oxygen bonds such as oxygen interstitials (Oi). Distributions of density of states in IGTO bandgap extracted by photonic capacitance-voltage measurement matched well with positive bias stress (PBS) instability of TFTs. Split-oxygen interstitials [Oi (split)] first created on IGTO by oxygen plasma might migrate to the octahedral site by a constant high gate bias to form octahedral-oxygen interstitials [Oi2- (oct)] by capturing electrons under PBS and reside deep states. Significant changes of subthreshold slope in I-V characteristics during the recovery time after removing PBS indicated that these octahedral-oxygen interstitials such as Oi (oct) and Oi2- (oct) obviously originated from Oi (split) initially formed by plasma and that Oi (oct) defects created by a relaxation process acted as a neutral acceptor-like state above Fermi level and deteriorated electrical properties of IGTO TFT.

Excitatory postsynaptic current model for synaptic thin-film transistors

Synaptic devices that mimic biological neurons have attracted much attention for brain-inspired neuromorphic computing. Especially, synaptic thin-film transistors (TFTs) have emerged with simultaneous signal processing and information storage advantages. However, the analysis of excitatory postsynaptic current (EPSC) relies on an empirical model such as a serial RC circuit, which limits a systematic and in-depth study of synaptic devices in terms of material and electrical properties. Herein, the single-pulse-driven synaptic EPSC (SPSE) model, including capacitive effect and information of the synaptic window, is analytically proposed. The SPSE model can simulate EPSC of synaptic devices at given TFT-operating conditions. EPSC with the SPSE model can be characterized with quantified parameters for the capacitive effects and the synaptic windows, which also depend on the electrical condition applied to TFTs. Various kinds of synaptic-TFTs with different gate insulators (e.g., SiO2 and ion-gel) are used to confirm the performance of the SPSE model. For example, the SPSE model can capture the long-term robustness of ion-gel-based TFTs with specific quantified parameters. In addition, the SPSE model enables the estimation of energy consumption, which can potentially be leveraged to compare the energy cost of EPSC fairly. The SPSE model can provide a guideline to understand the physical properties of synaptic TFTs.

Improvement in the electrical properties of a-IGZO TFTs by using PA-PI as a modification layer

High performance display requires thin film transistors (TFTs) to have better electrical characteristics. In this study, we used photoalignment polyimide (PA-PI) as the modification layer to modify the morphology of the insulating layer and improve the contact characteristics between the insulating layer and the active layer, so as to improve the electrical properties of amorphous Indium Gallium Zinc Oxide (a-IGZO) TFTs. The modified layer was prepared on the polymethylmethacrylate (PMMA) insulating layer and then irradiated with 254 nm UV polarized light. The anisotropy and surface morphology of the modified layer were investigated, and devices based on different insulating layer structures were prepared and tested. The typical device parameters of IGZO TFTs prepared under optimal conditions showed a high saturation mobility (μsat) of 9.68 cm2/V·s, the switching ratio was 1.01 × 105, the threshold voltage was 3.7 V, and the sub-threshold swing was 2.1 V/dec. The highest saturated carrier mobility μsat increased by 145% compared with PMMA single insulation layer devices.

The influence of post-annealing temperature on indium-silicon oxide thin film transistors

The room temperature sputtered Indium silicon oxide (ISO) thin-films were post annealed at various temperatures and studied for thin-film transistor (TFT) active channel layer application. The structural and optical properties of as-deposited and post-annealed ISO thin-films were analysed. XRD and HRTEM analysis revealed transformation of ISO thin film from amorphous nature to polycrystalline nature when post-annealed above 150 °C. The surface topography analysis indicated the presence of smooth surfaces for all ISO thin-films. ISO thin-films exhibited the average visible transmittance of 87% regardless of post-annealing temperature. The highest saturation mobility of 39.1 cm2/V.s was achieved for ISO TFT post-annealed at 200 °C. The obtained results show that post annealing temperature has significant influence on ISO TFT properties.

Performance enhancement of solution-processed InZnO thin-film transistors by Al doping and surface passivation

Solution-processed oxide semiconductors have been considered as a potential alternative to vacuum-based ones in printable electronics. However, despite spin-coated InZnO (IZO) thin-film transistors (TFTs) have shown a relatively high mobility, the lack of carrier suppressor and the high sensitivity to oxygen and water molecules in ambient air make them potentially suffer issues of poor stability. In this work, Al is used as the third cation doping element to study the effects on the electrical, optoelectronic, and physical properties of IZO TFTs. A hydrophobic self-assembled monolayer called octadecyltrimethoxysilane is introduced as the surface passivation layer, aiming to reduce the effects from air and understand the importance of top surface conditions in solution-processed, ultra-thin oxide TFTs. Owing to the reduced trap states within the film and at the top surface enabled by the doping and passivation, the optimized TFTs show an increased current on/off ratio, a reduced drain current hysteresis, and a significantly enhanced bias stress stability, compared with the untreated ones. By combining with high-capacitance AlO x , TFTs with a low operating voltage of 1.5 V, a current on/off ratio of > 10 4 and a mobility of 4.6 cm2/(V·s) are demonstrated, suggesting the promising features for future low-cost, low-power electronics.

Back-Channel Etched In-Ga-Zn-O Thin-Film Transistor Utilizing Selective Wet-Etching of Copper Source and Drain

The electrical performance of the back-channel etched Indium–Gallium–Zinc–Oxide (IGZO) thin-film transistors (TFTs) with copper (Cu) source and drain (S/D) which are patterned by a selective etchant was investigated. The Cu S/D were fabricated on a molybdenum (Mo) layer to prevent the Cu diffusion to the active layer (IGZO). We deposited the Cu layer using thermal evaporation and performed the selective wet etching of Cu using a non-acidic special etchant without damaging the IGZO active layer. We fabricated the IGZO TFTs and compared the performance in terms of linear and saturation region mobility, threshold voltage and ON current (ION). The IGZO TFTs with Mo/Cu S/D exhibit good electrical properties, as the linear region mobility is 12.3 cm2/V-s, saturation region mobility is 11 cm2/V-s, threshold voltage is 1.2 V and ION is 3.16 × 10−6 A. We patterned all the layers by a photolithography process. Finally, we introduced a SiO2-ESL layer to protect the device from external influence. The results show that the prevention of Cu and the introduced ESL layer enhances the electrical properties of IGZO TFTs.

Performance Enhancement of InGaZnO Top-Gate Thin Film Transistor With Low-Temperature High-Pressure Fluorine Treatment

In this work, the suppression of hydrogen diffusion in top-gate InGaZnO thin film transistors (TFTs) was observed. Under positive-bias temperature stress, the threshold voltage in short-channel devices was negatively shifted; this shift was attributed to hydrogen diffusion. To inhibit hydrogen migration, low-temperature high-pressure (LTHP) fluorine treatment was subsequently utilized. Under supercritical fluid states, fluorine, the most electronegative species of all elements, acted as a reactant and reduced mobile hydrogen. It was confirmed that the treatment benefited the characteristic properties of InGaZnO TFTs with varied channel lengths, especially in devices with short channels. The reliability of devices under stress improved through the LTHP treatment; the effects of suppression of hydrogen diffusion were illustrated by the energy band and capacitance–voltage curves of devices. Energy-dispersive X-ray spectroscopy of the specimen treated with LTHP indicated the presence of fluorine, which ensured the contribution of the treatment. Thus, LTHP treatment enables the realization of small-sized high-performance top-gate InGaZnO TFTs.

Performances of thin film transistors with Ga-doped ZnO source and drain electrodes

In this paper, indium-gallium-zinc-oxide thin film transistors (TFTs) were successfully fabricated by the pulsed laser deposition Ga-doped ZnO (GZO) films as source/drain (S/D) electrodes. And the GZO electrodes involved were prepared at room temperature. It was found that with the increase of Ga doping content, the electrical properties of TFTs increased first and then decreased. When the doping amount of Ga2O3 was 2 wt.%, the TFT showed excellent performance with a μ sat of 12.22 cm2V−1 s−1, an I on/I off of 6.4 × 107, a V on of 0 V and a SS of 0.082 V decade−1. At this time, the contact between the S/D electrodes and the active layer was ohmic and the TFT had a very low contact resistance with an R SD-eff of 0.064 Ω cm2. In addition, the device exhibited good electrical stability, and the drift of V on is only 2/−0.2 V at a positive/negative bias gate voltage of +10 V/−10 V with a duration of 5400 s under dark condition.