Properties Of Interconnects Research Articles

Transient Analysis of Shielded On-Chip Interconnections

Transients in shielded on-chip interconnections are studied theoretically for grounded and ungrounded shields. The model is based on analytical solutions to telegrapher's equations. The properties of interconnections and shields are identified that affect transients and propagation delays in signal lines. It is shown that cross coupling may exist between lines using a common shield. The magnitude of electromagnetic interference in shielded lines is estimated.

Electromigration in Submicron Dual-damascene Cu/low-k Interconnects

AbstractElectromigration (EM) lifetime characteristics and failure mechanism were investigated for Cu/porous-low-k interconnects and compared to Cu/oxide. The porous low-k dielectric was JSR LKD-5109TM, an MSQ-based spin-on organosilicate material with k = 2.2. The activation energies for EM failure were found to be 0.9 - 1.0 eV for the porous MSQ and 0.8 eV for oxide while the current density exponents for both materials were found to be similar, 1.2 - 1.3. This range of activation energies are commonly associated with mass transport at the Cu/cap-layer interface and suggest a similar mass transport mechanism; interfacial diffusion. Porous MSQ structures showed the same distinct failure morphology as observed in other Cu/low-k interconnects: voiding at the cathode and lateral Cu extrusion at the anode under the cap layer, which seems to be related to the thermo-mechanical properties of Cu/low-k interconnects. The shorter lifetime characteristics of Cu/low-k interconnects comparing to Cu/oxide can be attributed to a smaller back stress, due to less thermomechanical confinement. Results of this study indicate that thermo-mechanical properties of low-k interconnects are important parameters in controlling EM reliability of Cu/low-k interconnects.

Model Analysis of Transients in On-Chip Interconnections

Transient processes due to the inductive properties of interconnections are considered. The hierarchy of characteristic physical times is discussed at a qualitative level. From model solutions of the telegraph equations, a perturbation parameter is derived. It allows asymptotic representation in terms of the RLCand RCmodels of interconnections. Associated estimates for submicron technologies are given.

Computational Models of Thalamocortical Augmenting Responses

Repetitive stimulation of the dorsal thalamus at 7-14 Hz produces an increasing number of spikes at an increasing frequency in neocortical neurons during the first few stimuli. Possible mechanisms underlying these cortical augmenting responses were analyzed with a computer model that included populations of thalamocortical cells, thalamic reticular neurons, up to two layers of cortical pyramidal cells, and cortical inhibitory interneurons. Repetitive thalamic stimulation produced a low-threshold intrathalamic augmentation in the model based on the deinactivation of the low-threshold Ca2+ current in thalamocortical cells, which in turn induced cortical augmenting responses. In the cortical model, augmenting responses were more powerful in the "input" layer compared with those in the "output" layer. Cortical stimulation of the network model produced augmenting responses in cortical neurons in distant cortical areas through corticothalamocortical loops and low-threshold intrathalamic augmentation. Thalamic stimulation was more effective in eliciting augmenting responses than cortical stimulation. Intracortical inhibition had an important influence on the genesis of augmenting responses in cortical neurons: A shift in the balance between intracortical excitation and inhibition toward excitation transformed an augmenting responses to long-lasting paroxysmal discharge. The predictions of the model were compared with in vivo recordings from neurons in cortical area 4 and thalamic ventrolateral nucleus of anesthetized cats. The known intrinsic properties of thalamic cells and thalamocortical interconnections can account for the basic properties of cortical augmenting responses.

CMOS buffer sizing for long on-chip interconnects

A novel transistor sizing rule for long interconnect drivers is proposed. It allows true line matching to be achieved, thus either minimising delay or preserving signal integrity, when propagation time along the line becomes significant with respect to signal transition time. In this case the transmission line properties of long interconnects alter the behaviour of the CMOS buffer, forcing transistors to work mainly in the linear mode rather than in saturation as is usually assumed.

Evolution of the Electrical Properties of Interconnects Under Electromigration Stress

AbstractWe report experimental results of measurements of the changes in the resistance and thermal non-linearity of a variety of samples during accelerated electromigration stress to failure. The value of the extra measurement of the second harmonic of the AC bridge signal is illustrated by observations of changes in the thermal conductance to the substrate and the temperature coefficient of resistivity which are not detected by the resistance measurement. These quantities are also larger than the resistance measurement.

Flip chip attachment using anisotropic conductive adhesives and electroless nickel bumps

Flip chip attachments provide the highest interconnection density possible, which makes this technology very attractive for use with liquid crystal display (LCD) packaging methods. This technology stimulated the development of new interconnection techniques, such as anisotropic adhesives. However, several factors have hindered the wide use of this technology. These factors include the availability and costs of bumped wafers. IZM and TU-Berlin have addressed both of these concerns by establishing a wafer-bumping facility which uses electroless nickel bumps. The combination of anisotropic adhesives and electroless nickel bumps has the potential for a low-cost chip on glass (COG) and chip on flex (COF) bonding technology. In this paper, two types of anisotropic adhesives were studied with an emphasis on the properties of COG and COF interconnections. The electrical and mechanical performance of the adhesive bonds was studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity.

Dynamic properties of bulk power interconnections

The paper describes changes in dynamic properties of the present-day bulk electric power systems (EPS) in the course of their development, on the basis of operating experience and numerous studies. The character, reasons and consequences of these changes are analysed. The dynamic properties of EPS are becoming worse leading to a decrease in the reliability of consumer supply. Consideration is given to the emergency control measures that reduce the negative consequences for consumers in such systems.

A new anisotropic conductive film with arrayed conductive particles

A new anisotropic conductive film (ACF) incorporating arrayed metal conductors in an adhesive polymer film is proposed. A photoresist pattern with a number of round holes arrayed in triangular arrangement is formed on a stainless steel substrate. The holes are then electroplated to form metal bumps, using the substrate as a cathode. After removal of the photoresist, the substrate is laminated with a solid adhesive film. Finally, the ACF of arrayed metal bumps is obtained when the adhesive film is peeled off and the metal bumps are transferred from the substrate to the adhesive film. The superior interconnection properties of the proposed ACF, compared with conventional ACFs that rely on randomly distributed conductive particles, are attributed to the arrayed, uniformly sized particles in the adhesive film.

Designing and Building Reliability Into VLSI Interconnect Systems

ABSTRACTThe optimization of electromigration (EM) and stress-induced voiding (SV) properties of advanced interconnects impacts many critical system design parameters. In particular, the choice of materials and manufacturing processes must be carefully planned during the early phases of product development. In layered metallizations, both the barrier and capping layers design can affect electromigration resistance and stress-relaxation behavior, while electrical performance often constitutes a trade-off. This is shown specifically in a study of titanium diffusion into Al-Cu from TiN barrier layers, and in initial stress-relaxation tests characterizing the effect of Ti addition in the capping layer. The development of advanced characterization techniques supports the trial-and-error experimental optimization process, but models predicting EM and SV reliability are needed and should include complex sets of microstructural and design parameters.

HREM and AEM study of Pt/SiC interface annealed at high temperature

High temperature applications of SiC semiconductor devices will be essentially limited by the metal/SiC interface interconnect properties. Pt/SiC was reported to have more stable and better electrical properties than other metal/6H-SiC after annealing above 700°C under UHV condition. Some work on the Pt/SiC interface has been conducted by AES and other low spatial resolution surface techniques, but there is no detailed direct image data reported. Here, we characterize the microstructure of the Pt/SiC interface after high temperature annealing in UHV at near atomic resolution and reported the first nanospectroscopic energy loss data for the system.As-deposited Pt film is polycrystalline with grain size of 10 ± 3 nm (Fig.l). The thin amorphous layer visible at the interface in Fig.l, gradually disappearing in the thick regions, was attributed to oxygen-induced ion-milling damage. Similar results were observed frequently in other metal/ceramic system. We consider the amorphous layer to be due to residual oxygen on the ceramic surface during synthesis, since trace oxygen was only detected at the as-deposited Pt/6H-SiC interface.

The effect of scaling on contact and interconnect properties with sputtered TiSi 2 metallization

Investigations are made on contact and interconnect properties for scaling MOS transistor technology employing sputtered TiSi 2 metallization. The contact resistance of different contacts varying in size is measured for n + SiTiSi 2 shallow junction contacts using Kelvin test structures. It is found that the contact resistance almost doubles when the contact size is reduced from 5 to 2 microns. The results are compared with the conventional AlSi 2% contact metallization. The electrical and structural properties of n + poly SiTiSi 2 composite structures are studied as gate and interconnect metallization. The optimum conditions for doping thin poly-Si without affecting thin gate dielectric properties is given. The sheet resistance for the polycide structures is reduced to 2 ohm sq −1 from 40 ohm sq −1 for poly-Si structures for gate metallization. The thermal ability of structures is also examined and the results are discussed.

Transmission properties of balanced interconnections

The author develops simple equations for computing the characteristic impedances and crosstalk of both unbalanced and balanced interconnections in a lossless, homogeneous, microstrip configuration (signal conductors above a ground plane). The equations are applied to compare the crosstalk resulting from both types of interconnections having 4-mil conductor widths when the packaging density is three signals per 54 mils. Similar comparisons for other signal packing densities and impedances are also presented. It is shown that balanced interconnections are much more immune to noise pickup. Also, they are free of ground noise and radiate relatively little. A theoretical transformation is developed in order to apply the equations to conductors having rectangular or circular cross-sections. The equations yield values which agree well with experiment, and they can also be applied to help analyze the interconnections associated with fiber-optic transceivers, monolithic microwave integrated circuits, hybrid integrated circuits, and various multichip modules. The effect of the dielectric constant on crosstalk is also discussed. >

A fractal analysis of interconnection complexity

The emergent, collective properties of computer interconnections are shown to be characterized by a noninteger dimension D/sub i/, which is, in general, different from the system's Euclidean dimension. This dimension characterizes the properties of a fractal support, or substrate, on which interconnections are placed to provide communication throughout the system. The interconnection support also acts as a host for a multifractal spectrum of interconnection distribution processes which characterize the change in connectivity in moving from the backplane to the transistor level. The properties of fractal systems are investigated by attempting to minimize their total wire length using a simulated annealing algorithm. Systems whose interconnection dimension is approximately equal to their Euclidean dimension are shown to possess minimum wire length arrangements. These results are then interpreted in terms of a geometrical temperature T/sub i/=1/D/sub i/. This analysis indicates that the system passes through a phase transition at T/sub i/ approximately=1/2 and that attainable system temperatures are bounded by 1/3<or=T/sub i/<or=1. The consequences for simulated annealing are discussed.<<ETX>>

Microstructural Aspects of Interconnect Failure

The range of microstructural effects on thin film and interconnect properties is briefly described, and the improvement of interconnect reliability with increased strength is reviewed. We show that the strengthening effect of dispersed second phases depends on their resistance to coarsening during thermal treatments. The rapid coarsening of Θ phases during annealing and accelerated electromigration testing is reviewed, leading to a discussion of metallurgical factors which determine the coarsening behavior. We describe alloy systems expected to have reduced coarsening rates. We suggest that the recently reported increased reliability of Al-Sc interconnects is due to finely dispersed coherent phases which are particularly resistant to coarsening. The range of electromigration failure morphologies is illustrated with particular emphasis on transgranular slit failures. The failures are discussed in terms of diffusion pathways and models for failure.

ANALYSIS AND MODELING OF INTERCONNECTS FOR HIGH-SPEED DIGITAL APPLICATIONS

Abstract The electromagnetic modeling of packages and interconnects plays a very important role in the design of high-speed digital circuits, and is most efficiently performed by using computer-aided design algorithms. In the past two decades, researchers in the electromagnetic and microwave areas have strived to extend the knowledge of interconnection properties. Their efforts have resulted in models and analytical methods without which the development of reliable design tools would be impossible. Packaging and interconnects nowadays represent a critical area for the design of high-performance digital systems, and the work of these contributors is invaluable. This paper exposes the state-of-the-art in packaging technology and reviews the important steps in the development of analytical models, numerical methods and simulation techniques for the design of high-speed interconnections.

Studies on the Nucleation Behaviors of Precipitation in Aluminum Metallization

ABSTRACTIn order to simulate the precipitation effect during the aluminum metallization in the VLSI processing, an analytical model was constructed in this work. The nucleation behaviors of the silicon and copper precipitates within the aluminum - 1.0 weight percent silicon - 0.5 weight percent copper were studied. The volume free energies and interfacial energies were estimated, and the activation energy barriers for the precipitate formation were calculated. Silicon precipitate is more likely to nucleate than copper precipitate due to its lower interfacial energy and strain energy. The mechanical and electrical properties of the aluminum interconnects can be improved by the precipitate hardening.

Integral equation solution to the skin effect problem in conductor strips of finite thickness

The skin effect of single and coupled conductor strips of finite thickness is analyzed using the dyadic Green's function and the integral equation formulation. Galerkin's method is used to solve the integral equation for the dispersion characteristics. The effects of the geometrical and electrical parameters on the conductor loss are investigated. Results are compared with previously published data and shown to be in good agreement. This approach is very useful for analyzing the electrical properties of interconnects in high-performance computer circuitries. >

Experimental analysis of transmission line parameters in high-speed GaAs digital circuit interconnects

Transmission line properties of typical high-speed interconnects were experimentally investigated by fabricating and characterizing coplanar strips on semi-insulating GaAs substrates. The strips have thicknesses of about 2500 AA or 5000 AA and widths of 4, 6, or 8 mu m so as to be representative of on-chip interconnects in high-speed GaAs digital circuits. Measurements are carried out up to 18 GHz, and the pertinent line parameters, such as resistance, capacitance per unit length, and characteristic impedance, are extracted using the measured S-parameters. The measurement results confirm the quasi-TEM properties of such interconnects. In all cases, the measured distributed capacitance and inductance are sensitive to frequency whereas the resistance is found to increase as much as 38% for the widest and thickest conductors. >

A closed form analytical model for the electrical properties of microstrip interconnects

A simple model is presented based on closed-form analytical approximations for the resistance, capacitance, inductance, and conductance of a generic microstrip interconnect. Working in the frequency domain, all the low-frequency lumped circuit and high-frequency transmission line properties can be calculated. As examples, this model is applied to high-frequency reflectivity measurements on Teflon and FR4 printed circuit board microstrips. Agreement to better than 5% up to 1 GHz is obtained by using a dielectric constant of 2.20 and dissipation factor of 0.004 for the Teflon boards and a dielectric constant of 4.9 at 1 MHz with a constant dissipation factor of 0.022 for the FR4 microstrips. This model enables packaging engineers to evaluate the possibilities of an interconnect technology very simply on their personal computers (PCs).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>