Designing and Building Reliability Into VLSI Interconnect Systems

Abstract

ABSTRACTThe optimization of electromigration (EM) and stress-induced voiding (SV) properties of advanced interconnects impacts many critical system design parameters. In particular, the choice of materials and manufacturing processes must be carefully planned during the early phases of product development. In layered metallizations, both the barrier and capping layers design can affect electromigration resistance and stress-relaxation behavior, while electrical performance often constitutes a trade-off. This is shown specifically in a study of titanium diffusion into Al-Cu from TiN barrier layers, and in initial stress-relaxation tests characterizing the effect of Ti addition in the capping layer. The development of advanced characterization techniques supports the trial-and-error experimental optimization process, but models predicting EM and SV reliability are needed and should include complex sets of microstructural and design parameters.