Programmable Read-only Memory Research Articles

Characterization of Single Event Effect in a Radiation Hardened Programmable Read-Only Memory in a 130 nm Bulk CMOS Technology

The concept of memory that can only be read but cannot be changed seems strange at first. In reality, it is found that it has great application potential, such as the processor with a fixed purpose, the initial set value of the microprocessor BIOS, and these data are stored in Programmable Read-Only Memory (PROM) to quickly realize system functions. The PROM storage content is fixed, greatly simplifying his design. The radiation of space particles is the main factor causing the failure of the electronic system of spacecraft. The PROM storage array of the space electronic system is the most basic guarantee for the normal operation of the electronic system. The chip adopts domestic 130 nm standard technology of Complementary Metal Oxide Semiconductor (CMOS), Muller-C digital filter is used in the peripheral subsystem of PROM storage array, and the core cell uses Dual Interlocked Cell (DICE) and ring gate and other radiation hardening technologies to design a 32Kx8bit radiation resistant asynchronous programmable PROM. Pre-silicon of devices was verified by Technology Computer Aided Design (TCAD), and post silicon radiation verification was completed through radiation experiment. The post silicon radiation experiment showed that the total ionizing Dose (TID) capacity of the PROM chip was ≥100 Krad (Si), the critical value of single event upset (SEU) was ≥37.1 MeV·cm2/mg, the critical value of single event latch up was ≥98 MeV·cm2/mg, meeting the life requirements of the initial value storage of aerospace electronic systems. These performances ensure the reliable operation of the space electronic system after restart.

White Rabbit Expansion Board: Design, Architecture, and Signal Integrity Simulations

The White Rabbit protocol allows synchronization and communication via an optical link in an integrated, modular, and scalable manner. It provides a solution to those applications that have very demanding requirements in terms of synchronization. Field-programmable gate arrays are used to implement the protocol; additionally, special hardware is needed to provide the necessary clock signals used by the dual-mixer time difference for precise phase measurement. In the present work, an expansion board that allows for White Rabbit functionality is presented. The expansion board contains the oscillators required by the White Rabbit protocol, one running at 125 MHz and another at 124.922 MHZ. The architecture of this board includes two oscillator systems for tests and comparison. One is based on VCOs and another on crystal oscillators running at the desired frequencies. In addition, it incorporates a temperature sensor, from where the medium access control address is extracted, an electrically erasable programmable read-only memory, a pulse-per-second output, and a USB UART to access the White Rabbit IP core at the field-programmable gate array. Finally, to ensure the quality of the layout design and guarantee the level of synchronization desired, the results of the power and signal integrity simulations are also presented.

Method of solving single-event upset for heterogeneous dual field programmable logic gate array for infrared remote sensing camera in orbit

On-orbit reconstruction is a hotspot technology in the field of space infrared remote sensing cameras technology. Since the space infrared remote sensing cameras perform detection work under the space radiation environment, the core part of its image processing unit, which is a static random-access memory type field programmable logic gate array (FPGA), is susceptible to the impact of high-energy particles, especially during single-event upset events. The occurrence of point-like granular noise in remote sensing images will affect the normal imaging detection performance of the system, and even lead to abnormal timing of infrared detectors in severe cases, thereby affecting the normal operation of infrared remote sensing cameras. Aiming at the reliability requirements of the normal operation of space infrared remote sensing cameras in the space radiation environment, we propose a modular architecture of heterogeneous dual FPGA for XilinxVirtex-5 series FPGA, which carries out periodic refresh, reconstruction, and uploading of Virtex-5 series FPGA through antifuse FPGA. The antifuse FPGA periodically refreshes and reconstructs the Virtex-5 series FPGA from a one-time programmable read-only memory and injects the program into the program storage NOR flash device, and periodically refreshes and reconstructs the Virtex-5 series FPGA from NOR flash. This method can refresh and reconstruct the space infrared remote sensing camera in orbit. The in-orbit flight data verification shows that this method can effectively solve the impact of single-particle turnover event and improve the reliability of the infrared remote sensing camera in orbit operation.

A CNN-Based E-Nose Using Time Series Features for Food Freshness Classification

In this article, a convolutional neural network (CNN)-based electronic nose system is proposed, which utilizes time series features to classify the freshness of food. The electronic nose is composed of three elements: a highly sensitive miniaturized micro-electromechanical systems (MEMS) metal–oxide (MOX)–semiconductor gas sensor array, a complementary metal–oxide–semiconductor (CMOS) integrated circuit, and a CNN-based classification unit. The gas sensors exhibit exceptional sensitivity, low power consumption, and a small size. The interface circuit for sensor readout is fabricated using a standard 180-nm CMOS process, with an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.5$ </tex-math></inline-formula> mm. The interface chip mainly consists of an analog-to-digital converter (ADC), an electrically erasable programmable read-only memory (EEPROM), an oscillator (OSC), power management, a heater driver, and a digital control circuit. Fixed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}{(}{t}{)}$ </tex-math></inline-formula> exposures are taken at specific intervals under gas input and output conditions. Time series features are extracted from a diverse set of sensor signals, which allows the subtle differences in various food odors at different freshness levels to be identified. The incorporation of time series feature extraction extends the data features, resulting in enhanced classification accuracy with a limited number of sensors. An abstract odor map input to the CNN is formed by combining the steady-state and transient information of the gas sensor response. The final freshness classification accuracy of 20 types of foods is 97.3%. The accuracy is improved by 6.5% after the implementation of time series feature extraction, demonstrating the significance of instantaneous fluctuation information for classification accuracy.

BEOL-Compatible Bilayer Reprogrammable One-Time Programmable Memory for Low-Voltage Operation

In this work, an engineered submicrometer-scale bilayer stacking in via-type one-time programmable (OTP) memory and self-rectified resistive switching memory [resistive random access memory (ReRAM)] is demonstrated. The current development has achieved that co-existing memory functionality (OTP and ReRAM) with mitigating scaling requirement (fuse voltage trending with via size scaling), low fabrication complexity [via-fuse vs. gate-dielectric anti-fuse (AF)], and match with the current metal fuse technology ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$ </tex-math></inline-formula> 2 V). In addition, an electrode engineered has been proposed to realize low programming voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 1.9 V) in via-fuse OTP featuring by metal–insulator–metal advanced back-end-of-line (BEOL) process with ruthenium materials. The impact of via-size, programming window, stacked structures, and integration capability has been extensively studied. Our results provide a pathfinding of high density, integration capability, low programming voltage, multifunctionality between programmable read-only memory (PROM), and resistive switching memory co-existing in future embedded applications.

Precision Hall Effect magnetometer.

The article presents a Hall effect magnetometer for use in a desktop Electron Paramagnetic Resonance spectrometer with a permanent magnet system and scanning coils. High accuracy and long-term stability at a small size and low cost are achieved through the use of digital signal processing, sequential data filtering in the time and frequency domains, as well as digital correction of raw data based on calibration information. The exciting current of the Hall sensor has the form of an alternating-signsquare wave formed by a high-speed H-bridge powered by a stable direct current. Generation of control signals, time selection of data, and their accumulation are performed using Xilinx Field-Programmable Gate Array Artix-7. MicroBlaze embedded 32-bit processor is used to control the magnetometer and interface with adjacent levels of the control system. Taking into account the individual characteristics of the sensor, including the offset voltage, the nonlinearity of the magnetic sensitivity, and their temperature dependences, is carried out by correcting the data obtained by calculating a polynomial depending on the raw magnitude of the field induction and the temperature of the sensor. The polynomial coefficients are individual for each sensor, are determined once during the calibration process, and are stored in the dedicated Electrically Erasable Programmable Read-Only Memory. The magnetometer has a high resolution of 0.1 µT and an absolute measurement error of not exceeding 6 µT.

Experimental Study of Transient Dose Rate Effect on System-in-Package SZ0501

This article investigates the transient dose rate effect (TDRE) on the system-in-package (SiP) SZ0501 experimentally. A specialized program is designed for TDRE tests. With the increase of dose rates, the failure features of the SiP are recorded. Photocurrents on each power supply line are also measured to assist in analyzing SiP failures. In addition, both enabled and disabled programmable read-only memory (PROM) cases are considered to compare their discrepancies. The experimental results show that high frequency (HF) signals in the SiP are much sensitive to TDRE. Also, the logical resource in its field-programmable gate array (FPGA) presents a higher sensitivity than the clock resource, which is a contrary finding to the previous results. Besides, it is found that there seems to be a micro latch-up window in the SiP. Moreover, this SiP demonstrates different TDRE for enabled PROM and disabled PROM cases, and it has an automatic reconfiguration process in the case of enabled PROM. These findings are followed by a detailed analysis and discussion.

Bifunctional HfOx-based Resistive Memory: Reprogrammable and One-Time Programmable (OTP) Memory

The dual functions in HfOx-based ReRAM and 2V-programmable via-fuse technology featuring in simple metal-insulator-metal BEOL process are presented, which can integrate with the current metal fuse technology. The impact of via-size, ReRAM, and via-fusing programming windows, stacked structures, and integration capability has been extensively studied. The performance and reliability risk assessments show that the ReRAM and via fuse can sustain at 438 K for 500 h without any degradation. Our results provide pathfinding of high density, integration capability, low programing voltage, multi-functionality between programmable read-only memory (PROM) and ReRAM co-existing in embedded applications.

THE ENHANCEMENTS IN STORAGE CAPACITY AND LONG-TERM DATA RETENTION OF MULTIDIMENSIONAL FLASH MEMORY IN MODERN MICROCIRCUIT APPLICATIONS

Generally, flash memory is a type of permanent memory for computers in which the contents can be reprocessed or erased electronically. Compared to programmable read-only memory that can erase electricity, operations on it can be performed on modules located in different locations. Flash memory is much less expensive than EEPROM, which is why it has become a dominant technology. Especially, in situations, this stable and long-term data retention is required. Its use is allowed in various cases like digital audio players, photo and video cameras, mobile phones and smartphones, and specialized Android applications on the memory card. Additionally, it is also used on USB flash drives, traditionally used to store and transfer information between computers. The proposed model provides enhancements to the storage capacity of various flash memory modules. In a saturation point, the proposed model achieved 93.03% of NOR Memory management, 89.31% of NAND Memory management, 94.25% of Ferroelectric RAM Memory management, and 94.53% of Magnetic RAM Memory management, 96.05% of Ovonic Unified Memory management and 96.16% of Salcogenide RAM Memory management.

Mesin Penetas Telur Menggunakan Microcontroller ATMega328 Berbasis Arduino

The purpose of this study was to design and implement a duck egg incubator. An egg incubator is a machine that functions to take over the incubation task of a duck mother in incubating fertilized eggs from the result of crossing or mating with a male. The existing incubators work in temperature control, reversing the egg racks, but do not use an egg informing system that has been hatched. In designing this duck egg incubator based on Arduino as a controller. The temperature used must be measured by the resistance of the space or the approximate resistance of the eggs to hatch. The microcontroller used is the ATMega328 integrated on the Arduino Uno, temperature sensor, humidity sensor, humidity control system and other supporting components using Arduino. The test was carried out by comparing the DS18B20 temperature sensor with a Thermometer with an error difference of 0.15. The result of this research is the device can control the temperature not exceeding 39 ° C for hatching eggs. The device has 2 usage buttons, namely a start button (green) to perform hatching day calculations and a reset button (red) to stop hatching day calculations. The day variable that has been running is still stored in the microcontroller EEPROM (Electrically Erasable Programmable Read-Only Memory) so that if there is a disconnection or loss of a voltage power source such as a power failure and so on. The 12VDC fan on the device turns on every 30 minutes and goes out for the next 30 minutes

A Digital Improvement-Trimming a Digital Temperature Sensor with EEPROM Reprogrammable Fuses.

An EEPROM (electrically erasable programmable read-only memory) reprogrammable fuse for trimming a digital temperature sensor is designed in a 0.18-µm CMOS EEPROM. The fuse uses EEPROM memory cells, which allow multiple programming cycles by modifying the stored data on the digital trim codes applied to the thermal sensor. By reprogramming the fuse, the temperature sensor can be adjusted with an increased trim variation in order to achieve higher accuracy. Experimental results for the trimmed digital sensor showed a +1.5/−1.0 ℃ inaccuracy in the temperature range of −20 to 125 ℃ for 25 trimmed DTS samples at 1.8 V by one-point calibration. Furthermore, an average mean of 0.40 ℃ and a standard deviation of 0.70 ℃ temperature error were obtained in the same temperature range for power supply voltages from 1.7 to 1.9 V. Thus, the digital sensor exhibits similar performances for the entire power supply range of 1.7 to 3.6 V.

Design of Phototherapy Radiometer with a Measurement Stability Improvement

The amount of radiation given from the phototherapy lamp (Blue Light) who not right for neonates with hyperbilirubin is feared to cause the bilirubin levels in not decrease accordance with the calculated dose. The purpose of this study is to make a Blue Light calibration device with a stable measurement. The contribution of this research is by determine a sensor who able to measure the irradiation value more accurately between TCS3200 and AS7262 sensor. TCS3200 sensor measures the wavelengths of 470nm, 524nm and 640nm and AS7262 sensor can measure wavelengths of 430-670nm. The results of both sensors are stored in the Electrically Erasable Programmable Read-Only Memory, with the amount of data and the length of measurement can be adjusted according to user needs. Measurement the irradiation value of two sensors is done simultaneously using 3 Watt Light Emitting Diode lamp as a Blue Light simulation where the lamp is placed directly above the sensor and distance of the lamp to the sensor is 10cm, 20cm, 30cm, and 40cm. The average uncertainty value with TCS3200 sensor is 14.65 and the average uncertainty value with AS7262 sensor is 2.17. Type A uncertainty value is based on results of repeated measurements that show how close the measurement results are to the actual value (stable measurement results). The results showed that the average uncertainty value on AS7262 sensor is relatively small, so its mean the measurement results of AS7262 sensor are stable. The author suggests using sensors who capable of reading the value of light radiation without conversion. The results of this study can be implemented to measure the intensity of the lamp and be used as a reference to determining the time of lamp replacement.

Integrated Prognostics Observer for Condition Monitoring of an Automated Manual Transmission Dry Clutch System

The closed loop feedback control system of an Automated Manual Transmission (AMT) electro-pneumatic clutch actuator is used for intelligent real time condition monitoring, enhanced diagnostics and prognostic health management of the dry clutch system, by integrating with the existing gearbox prognostics observer. The real-time sensor data of the clutch actuator piston position is analyzed for monitoring the condition of the clutch system. Original parameters of the new clutch are stored in the Electrically Erasable Programmable Read-only Memory (EEPROM) of the AMT controller and the real-time data is used by the observer for assessing the degradation/wear of the frictional clutch parts. Also, clutch slip during torque transmission is monitored, using the engine speed and the gearbox input shaft speed from Controller Area Network (CAN). Condition monitoring of clutch system provides enhanced prognostic functionality for AMT system which ensures consistent clutch performance, gear shift quality and timely warning for recalibration, repair and/or replacement of the critical wear and tear parts. Also, systematic analysis of the monitored data provides an accurate diagnosis of a developing fault. Thus, with the advanced control systems in place for AMT, a closed loop feedback based condition monitoring system is modelled for improved diagnostics and prognostics of AMT clutch system.

Restoring Stephan Von Huene's Tap Dancer: Finding Logic within Integrated Circuits

ABSTRACT Stephan von Huene is recognized for his acoustical sculptures that combine movement and sound with the flip of a switch. This paper will focus on his Tap Dancer (1967) composed of cropped legs in pants and shoes on a wooden base that perform a 30-second tap dance at regular intervals. The movement and sound are controlled by integrated circuit boards wired to valves, a vacuum and recycled musical components. The condition of the wiring and circuitry is critical to allow the performance, which is intended to be random by way of an erasable programmable read-only memory (EPROM) and timing circuit. Von Huene's sculptures have conservation issues when exhibited and plugged in for action. Challenges arose during the exhibition of Tap Dancer at the J. Paul Getty Museum in Los Angeles leading to conservation interventions including the adaptation of EPROM data to a solid-state controller. After exhibition at the Getty, the temporary solutions were replaced with a full restoration of the original circuit boards repairing wiring or damaged chips as needed. The history of Tap Dancer has shown that with the desire to exhibit von Huene's works as intended, the endurance of their structures is inevitably at risk.

A system verilog approach for verification of memory controller

&lt;span&gt;Memory performance has become the major bottleneck to improve the overall performance of the computer system. By using memory controller, there is effective control of data between processor and memory. In this paper, a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint random verification environment is built for the designed memory controller. Verification plays an important role in any design flow as it is done before silicon development. It is done at time of product development for quality checking and bug fixing in design.&lt;/span&gt;

A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM.

A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID–EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non- overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 μW at 10.2 MHz and that the phase noise was only -119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 μW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to <4 mV. Therefore, the integration of all the proposed modules in HVG ensured low-ripple programming voltages, higher pumping efficiency, and EEPROMs with lower power dissipation, and can be extensively used in low-power applications, such as in non-volatile memory, radiofrequency identification transponders, on-chip direct current DC-DC converters.

Innovative and rapid design for I2C (inter-integrated circuit) interface communication of FPGA chips

A new design flow is proposed to greatly improve the efficiency and accuracy of the HDL program design. This paper successfully completes the FPGA (Field-Programmable Gate Array) chip’s external communication I2C interface design of new design flow not traditionally one. FPGA chip is often used in mobile phones, military, aerospace or other industries. Even INTEL and Microsoft and other large companies have begun to acquire FPGA-related companies, showing its importance. But the FPGA language is written in the Hardware Description Language (HDL) which is a mechanical engineering staff obstacles. Therefore, this article makes use of the MATLAB / SIMULINK tool, which is familiar with the engineering staff, to complete the FPGA chip’s I2C interface design. The advantage is that the functional simulation and HDL program can be completed at the same time, do not have to perform the function after the simulation before designing HDL program. The traditional design wastes many times to revise back and forth between function simulation and HDL program design. Finally an experimental illustration is proposed to verify the proposed design of the I2C communication interface for an HDL program on the read and write experiments of Electrically-Erasable Programmable Read-Only Memory (EEPROM).

Hardware and software integrated coursework as a way of engineering ability training in the learning of digital electronics

A new way oriented to engineering ability training by field programmable gate array-based hardware and software integrated coursework in the learning of digital electronics course in communication engineering is presented. This coursework is implemented in two stages during six weeks, the task of the first stage is hardware design, and the second stage task is the software design; all students are divided into several small teams with three or four persons in the process. A scheme for storing and configuring four different programs by a single programmable read-only memory (PROM)is given in hardware design. In the software design, it emphasizes the selection of the optimization scheme for different design schemes. Through competitive and engineering oriented design evaluation, the students are guided to combine theory with practice more closely to solve the actual engineering problems in the design.

An efficient Verilog-A memristor model implementation: simulation and application

Complementary metal–oxide–semiconductor (CMOS) technology is reaching its limits due to the continuous shrinking process, which has an impact on various aspects including device size, performance, and power consumption. The memristor is one of the promising devices under investigation for use with deep-nanometer CMOS, having applicability in several fields due to its nonlinear behavior, nonvolatility, low power consumption, high density, and CMOS compatibility. Several models for memristors have been developed to date, but there is a requirement for compact models that are both flexible and sufficiently accurate. A general memristor model generated in Verilog-A is discussed herein to confirm its behavior in the one-transistor one-resistor (1T1R) oxide-based random-access memory (OxRAM) configuration, and validated at circuit level. The results of the model correlate well with experimental characterization data for the HfO2-based OxRAM memristor device, describing the characteristics of both its bipolar and unipolar memristor behaviors. The 1T1R structure is analyzed using the Spectre circuit simulator. Two cases are considered, using the cell as either programmable read-only memory (PROM) or electrically erasable programmable read-only memory (EEPROM). The simulation results confirm the desired nonlinear memristor characteristic, and the applicability of the model to fit and simulate different switching behaviors. The results are verified against both electrical and experimental characterization data, suggesting that the Verilog-A model is suitable for low-power and high-density logic circuit applications at the industrial level.

Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.