Programmable Logic Blocks Research Articles

Eğitsel SDR Tekniklerine Dayalı FPGA Tabanlı FM Radyo Verici Tasarım ve Uygulaması

The basic purpose of Software Defined Radio (SDR) systems is to use a digital signal processor to numerically handle radio signals. The use of a processor like a Field Programmable Gate Array (FPGA) to perform tasks like modulation, demodulation, signal creation, and line coding on these systems dramatically decreases the demand for analog circuit-based hardware. FPGAs are digital integrated circuits with a wide range of applications which are made up of links between programmable logic blocks. It's aimed at assisting the creator realize the logic functions that the designer needs. In consequence, the user may change the function of each logic block. VHSIC Hardware Description Language (VHDL) is commonly used in FPGA programming. In this study, VHDL code was created, and a FM transmitter was implemented on a FPGA board (CMOD A7) in this research. The sound card interface on the PC used to send and receive the signals while suitable ADC and DAC cards are used on the FPGA side for the same purpose. Audacity program was used to playback the sample wav files while HDSDR SDR program was used to monitor and record the signals in wav file format. Finally, using the MATLAB code, the recorded transmitter signal was demodulated offline, and the output was stored to the hard drive. The demodulated signal obtained is identical to the initial modulation signal, indicating that the modulation was correctly executed. As a result, a perfect foundation for the development and training of SDR systems using FPGA has been established.

THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell&#x2013;along with the symmetry of the mask- and field-programmable gate array logic cells&#x2013;made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric.

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and real‐time‐integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS) technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article focuses on the design and development of hybrid delay‐controlled reconfigurable ALU (DCR‐ALU) using field‐effect transistor (FinFET) and graphene nanoribbon field‐effect transistor (GnrFET) technologies. Initially, a novel carry output predictable full adder (COPFA) and carry input selectable full adders (CISFA) are developed using multiplexer selection logic; then, delay‐controlled hybrid adder (DCHA) and delay‐controlled hybrid subtractor (DCHS) are developed using these full adders. In addition, a unified delay‐controlled hybrid adder and subtractor (DCHAS) is developed by combining these DCHA and DCHS. Further, a delay controller array multiplier (DCAM) also developed using DCHA modules. Finally, DCR‐ALU is developed by adopting the DCHAS, DCAM, and logical operations. The obtained simulation results shows that the proposed nanotechnology‐based models outperformed the conventional adders and subtractors in terms of area, power, and delay reduction.

Digital-to-time converter for test equipment implemented using FPGA DSP blocks

This paper presents a novel digital-to-time converter (DTC) implemented using digital signal processing (DSP) blocks built in field-programmable gate array (FPGA) devices. The converter was implemented in a low-cost Xilinx Spartan-6 FPGA chip manufactured in the 45 nm CMOS process and can be applied in any other programmable logic device that contains DSP blocks. The designed DTC time interval jitter is below 2.8 ps. This is the lowest time interval jitter so far reported in such kind of circuits implemented in a programable device. The obtained resolution of up to 8.6 ps is about twice as good as that achieved in a single carry-chain-based delay-line. Furthermore, the designed circuit saves FPGA general-purpose logic (programmable logic blocks). This kind of converter can be especially useful as a part of test instrumentations as well as time-domain signal processing systems implemented in the latest generation of programmable logic devices.

FPGA based real-time epileptic seizure prediction system

The development of systems that can predict epileptic seizures in real-time offers great hope for epilepsy patients. These systems aim to prevent accidents that patients may experience caused by the loss of consciousness during seizures. Therefore, patients must use real-time epileptic seizure prediction systems that do not interfere with their daily activities. In this study, using the unipolar EEG data from a surface electrode, a patient-specific estimation system is implemented in real-time on a system on chip (SoC) that contains an embedded processor and programmable logic blocks. The European epilepsy database EPILEPSIAE is used in the scope of this work. In the proposed system, pre-processing is applied to the EEG data. Then, the features of the data in the frequency domain are extracted. The classifier model is trained with the RusBoosted Tree cluster classifier, which is a machine learning algorithm. Testing is carried out using the proposed classification model. Threshold values are determined, and then false alarms and erroneous classifications are prevented by post-processing. At the end of the tests, prediction success, sensitivity (SEN), Specificity (SPE), False Prediction Rate (FPR), and prediction times are obtained as 77.30%, 95.94%, 0.041 h−1, and 33.23 min, respectively. The proposed system outperforms other studies in the literature in the number of electrodes, real-time operation, hardware/software architecture, and FPR performance. A wearable seizure prediction system seems to be commercialized according to the results achieved in this study.

Методы анализа выполнимости булевых формул для современных задач систем автоматизации проектирования в микроэлектронике

Currently, the methods based on a Boolean satisfiability (SAT) problem are one of the efficient approaches to solving the problem of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, the SAT methods demonstrate the results exceeding the classic routing algorithms by the operation speed and the quality of obtained results. In the paper, the analysis of the modern practice of using the SAT methods in the CAD systems for VLSI has been performed. The examples of modern SAT approaches to the problems of the formal equivalence checking of digital circuits descriptions within the technological mapping framework and to the routing problem as a part of the FPGA design flow have been considered. The algorithm of the detailed routing of the FPGA switching blocks using the satisfiability problem has been developed and presented. The results of its work have been demonstrated on the example of the programmable logic block of the domestic made integrated circuit 5400TP094. The block has the island architecture, where the configurable logic blocks and switching blocks form a regularly repeated layout template. The properties of the chosen classic architecture permit to expand the region of presented algorithm to the entire class of island style FPGA. The algorithm has been tested on the project benchmarks ISCAS-85, ISCAS-89 and LGSynth-89. The comparison of the developed SAT-based algorithm with the well-known routing algorithm Pathfinder by criteria of the elapsed time and the achieved portion of routed nets in the switching blocks is presented. It has been determined that the considered Boolean satisfiability methods for the routing problem are capable to prove the circuit unroutability, unlike the algorithm Pathfinder which results can only implicitly indicate it. The paper demonstrates that the application of more efficient SAT solver significantly accelerates work of the suggested detailed routing algorithm.

Efficient Implementation of Multiple Time Coding Lines-Based TDC in an FPGA Device

This article presents two principles that make multiple time coding lines (TCLs)-based time-to-digital converter (TDC) implementation in field-programmable gate array (FPGA) device more efficient. A pseudo-segmented delay line allows for saving many logical resources by effective utilization of programmable logic block elements. A chopped TCL improves measurement resolution and precision and takes advantage of a global clock network skew. Both designs were implemented in a Kintex-7 FPGA chip, manufactured by Xilinx in 28-nm CMOS process, and compared to well-known TCL solutions, that is, a commonly used “plain” architecture and a tuned delay line. All four designs, working in a single and multiple configurations, were tested and compared in terms of resource utilization, measurement resolution, and precision. Designed TDCs employed in a one channel timestamps-based interpolating time counter allowed to get mean resolution of 1 ps and precision even below 4 ps using up to ten TCLs.

Providing Reliability of Physical Systems: Partially Programmable Circuit Design

One of the important properties of physical systems is reliability.of their functioning, in particular, reliability of functioning of logical control components of the systems. A new approach to partially programmable circuit design that allows masking stuck-at faults at gate poles of logical circuits is considered. The logical circuit consists of gates. It is supposed that only one gate pole may be fault. There are reserved programmable blocks configurable logic blocks (CLBs) based on Look Up Table (LUT) technology that may mask the fault. First, the suggested approach in contrast to the well-known ones, allows masking any stuck-at fault rather than a part of them. Second, the approach is oriented to deriving more simple masking circuit from CLBs based on a compact description of incompletely specified functions of subcircuits.

Technology Mapping for Heterogeneous FPGA in Different EDA Stages

In traditional EDA flow, Technology mapping is performed after logic synthesis. Besides programmable logic blocks, heterogeneous FPGAs also have some hard blocks, such as memory block and multiplier, built in it. After logic synthesis, it will be difficult for technology mapping to find sub-circuits that can be implemented in hard blocks. In this paper, a systematic technology mapping approach is proposed. In the design phase, with the support of CAD tools, a module based design approach is used to map some design block to large hard blocks. During register transfer level synthesis, some functions that are suitable to be implemented in small hard blocks are identified. Other logic functions are mapped into lookup tables with different input size.

Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some programmable logic concepts into an introductory digital electronics course is presented. The proposed optional lab develops a printed circuit board that implements a programmable logic block. Another contribution is the collaborative problem-solving methodology used to achieve this goal. Surveys completed by the students, and their final grades, show that the lab has improved the quality of their education and has contributed to a successful integration of programmable logic concepts in an introductory digital electronics course. Because of its demands on students' time and effort, the lab favors the most motivated students. This suggests future research on a proposal for a lab that would be feasible within the time constraints for even the least motivated students.

Guest Editorial: Field-Programmable Technology

Field-Programmable Technology (FPT) describes those electronic systems where the hardware as well as the software can be programmed on an application by application basis. Field Programmable Gate Arrays (FPGAs) represent the most common form of FPT, widely used in applications such as signal and image processing, telecommunications and computer networking. FPT continues to intrigue researchers; current research ranges from transistor-level programmable logic, through to high performance applications, and encompasses the design methodologies and design tools needed for such systems. In “Reconfigurable Blocks Based on Balanced Ternary,” Paul Beckett and Tayab Memon describe a new programmable logic block which takes advantage of some of the unique characteristics of Silicon-onInsulator in order to deliver balanced ternary (−1,0,+1) logic functions and memory cells. In “Using Data Contention in Dual-ported Memories for Security Applications”, Tim Guneysu investigates the problem of how to protect design IP in a technology where hardware programs are difficult to secure. His paper explores device-specific behaviour during write collisions in dual-port FPGA memories to support IP protection. For embedded systems that use floating point arithmetic, the choice has been fast hardware or slow software implementations. In “Improving Floating-Point Performance in Less Area: Fractured Floating Point Units (FFPUs),” Neil Hockert and Katherine Compton look at partial hardware support for floating point, which gives better performance than software floating point, and lower area than a full hardware unit. As logic circuits get larger, the time for physical design at logic level discourages broad exploration of high-level architectural design alternatives. In “Rapid Synthesis and Simulation of Computational Ciruits in an MPPA,” David Grant, Graeme Smecher, Guy Lemieux and Rosemary Francis present a tool flow (RVETool) for rapidly compiling computational circuits into a Massively Parallel Processor Array. In “Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms,” Qiang Lie, Tim Todman, Wayne Luk and George Constantinides explore using FPGAs effectively for large computational problems. Having identified that many applications use a “MapReduce” computational pattern, they develop a L. Shannon (*) School of Engineering Science, Simon Fraser University, Burnaby, Canada e-mail: lshannon@ensc.sfu.ca

In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults

For anti-fuse or flash-memory-based field-programmable gate arrays (FPGAs), single-event transient (SET)-induced faults are significantly more pronounced than single-event upsets (SEUs). While most existing work studies SEU, this paper proposes a retiming algorithm for mitigating variational SETs (i.e., SETs with different durations and strengths). Considering the reshaping effect of an SET pulse caused by broadening and attenuation during its propagation, SET-aware retiming (SaR) redistributes combinational paths via post layout retiming and minimizes the possibility that an SET pulse is latched. The SaR problem is formulated as an integer linear programming (ILP) problem and solved efficiently by a progressive ILP approach. In contrast to existing SET-mitigation techniques, the proposed SaR does not change the FPGA architecture or the layout of an FPGA application. Instead, it reconfigures the connection between a flip-flop and an LUT within a programmable logic block. Experimental results show that SaR increases mean-time-to-failure (MTTF) by 78% for variational SETs with a 10-min runtime limit while preserving the clock frequency on ISCAS89 benchmark circuits. To the best of our knowledge, this paper is the first in-depth study on FPGA retiming for SET mitigation.

Accelerating Boolean Matching Using Bloom Filter

Boolean matching is a fundamental problem in FPGA synthesis, but existing Boolean matchers are not scalable to complex PLBs (programmable logic blocks) and large circuits. This paper proposes a filter-based Boolean matching method, F-BM, which accelerates Boolean matching using lookup tables implemented by Bloom filters storing pre-calculated matching results. To show the effectiveness of the proposed F-BM, a post-mapping re-synthesis minimizing area which employs Boolean matching as the kernel has been implemented. Tested on a broad selection of benchmarks, the re-synthesizer using F-BM is 80X faster with 0.5% more area, compared with the one using a SAT-based Boolean matcher.

Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate

Small gates, such as AND2, XOR2, and MUX2, have been mixed with lookup tables (LUTs) inside programmable logic blocks (PLBs) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macrogates with wide inputs inside PLBs is beneficial. In this paper, we first develop a methodology to extract a small set logic functions that are able to implement a large portion of functions for given FPGA applications, and propose a heterogeneous PLB with one LUT and one macrogate for the selected logic functions. Furthermore, we develop a synthesis flow for such heterogeneous PLBs, including a cut-based delay and area optimized technology mapping, a mixed binary integer and linear programming-based postmapping area recovery to balance the utilization of macrogates and LUTs, and a SAT-based PLB architecture-aware packing. Experiments using over 70 industrial benchmark applications show that we can extract four six-input logic functions to cover more than 50% functions of these applications, and the proposed synthesis flow reduces area by 5% compared to an alternative flow without the postmapping area recovery when both have the optimal logic depth. Compared to the PLB with mixed LUT-4 and small macrogates (XOR2 and MUX2), the PLB with mixed LUT-4 and four-input macrogate reduces logic depth by 6% (and up to 42%) for the aforementioned applications.

Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing

We present novel and efficient methods for built-in self-test (BIST) of field-programmable gate arrays (FPGAs) for detection and diagnosis of permanent faults in current, as well as emerging, technologies that are expected to have high fault densities. Our basic BIST methods can be used in both online and offline testing scenarios, although we focus on the former in this paper. We present 1- and 2-diagnosable BISTer designs that make up a ROving TEster (ROTE). Due to their provable diagnosabilities, these BISTers can avoid time-intensive adaptive diagnosis without significantly compromising diagnostic coverage-the percentage of faults correctly diagnosed. We also develop functional testing methods that test programmable logic blocks (PLBs) in only two circuit functions that will be mapped to them as the ROTE moves across a functioning FPGA. We extend our basic BISTer designs to those with test-pattern generators (TPGs) using multiple PLBs to more efficiently test the complex PLBs of current commercial FPGAs and to also prove the diagnosabilities of these designs. Simulation results show that our 1-diagnosable functional-test-based BISTer with a three-PLB TPG has very high diagnostic coverages-for example, for a random-fault distribution, our nonadaptive-diagnosis methods provide diagnostic coverages of 96% and 88% at fault densities of 10% and 25%, respectively, whereas the previous best nonadaptive-diagnosis method of the STAR-3 t 2 BISTer has diagnostic coverages of about 75% and 55% at these fault densities.

OPTIMAL LOGIC SYNTHESIS OF COMBINATIONAL CIRCUITS USING K-LUT FPGA

Determining if a given arbitrary, wide function can be implemented by a programmable logic block, is unfortunately, in general, a very difficult problem, called the Boolean matching problem. We introduce a novel implemented algorithm able to map for performance combinational networks using k-LUT based FPGAs. We consider in this paper delay optimum and area optimal k-LUT FPGA mapping algorithms and compare them against a newly developed and recently improved algorithm.

FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability

This paper presents a field-programmable gate array (FPGA) logic synthesis technique based upon Boolean satisfiability. This paper shows how to map any Boolean function into an arbitrary programmable logic block (PLB) architecture without any custom decomposition techniques. The authors illustrate several useful applications of this technique by showing how this technique can be used for architecture evaluation and area optimization. When evaluating the FPGA architecture, the authors focus on the basic building block of the FPGA, which they refer to as PLB. In order to illustrate the flexibility of their evaluation framework, several unrelated PLB architectures are evaluated in an automated fashion. Furthermore, the authors show that using their technique is able to reduce FPGA resource usage by 27% on average in common subcircuits found in digital design.

FPGA programmable logic block evaluation using quantified Boolean satisfiability

A novel field programmable gate array (FPGA) logic synthesis technique that determines if a logic function can be implemented in a given programmable circuit is presented, and how this problem can be formalised and solved using quantified Boolean satisfiability is described. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has many applications to FPGAs. The application demonstrated is the FPGA programmable logic block evaluation and the results show that this tool allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way.

Online BIST and BIST-based diagnosis of FPGA logic blocks

We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs) in the FPGA during normal system operation. The BIST-based diagnosis can identify any group of faulty PLBs, then applies additional diagnostic configurations to identify the faulty look-up table or flip-flop within a faulty PLB. The ability to locate defective modules inside a PLB enables a new form of fault-tolerance that reuses partially defective PLBs in their fault-free modes of operation.

BIST-based test and diagnosis of FPGA logic blocks

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.