Programmable Finite Impulse Response Filter Research Articles

Design and Performance Analysis of RNS-Based Reconfigurable FIR Filter for Noise Removal in Speech Signals Applications

In DSP solutions, the Residual Number System with Two's Complement systems is the most commonly utilized system for building low-power and high-throughput programmable Finite Impulse Response filters. It would be done by creating FIR filters in the Residual Number organization and 2's Enhance scheme by comparing the results to the current assert. The RNS based on FIR filter architecture reduces power consumption while allowing the device to operate at 150 MHz without increasing its size significantly. In case of memory and latency reduction, the implementations of the Residual Number System and 2's Complement System must be able to obtain and decode signals with fewer physical servers for every clock signal. The principal idea of this proposed model is to provide data bits with larger sizes for RNS-based multiplier and delayed wavelet LMS (DWLMS) that operates at speed high with premised reconfigurable FIR via forward and reverse conversions that don't produce as much power output and size as reflective thinking. The Application Specific Integrated Circuit will be designed and integrated for 32 nm technology. The proposed design addresses the four essential parameter optimization, such as power, area, and timing, using the Residual Number System, which is superior to Two's Complement System. According to the findings, there is a 13 percent reduction in power, a 21 % enhancement in area, and a 13 % enhance in throughput.

Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System

Coefficient multipliers are the stumbling blocks in programmable finite impulse response (FIR) digital filters. As the filter coefficients change either dynamically or periodically, the search for common subexpressions for multiplierless implementation needs to be performed over the entire gamut of integers of the desired precision, and the amount of shifts associated with each identified common subexpression needs to be memorized. The complexity of a quality search is thus beyond the existing design algorithms based on conventional binary and signed digit representations. This paper presents a new design paradigm for the programmable FIR filters by exploiting the extended double base number system (EDBNS). Due to its sparsity and innate abstraction of the sum of binary shifted partial products, the sharing of adders in the time-multiplexed multiple constant multiplication block of the programmable FIR filters can be maximized by a direct mapping from the quasi-minimum EDBNS. The multiplexing cost can be further reduced by merging double base terms. Logic synthesis results on more than one hundred programmable filters with filter taps ranging from 10 to 100 and coefficient word lengths of 8, 12, and 16 bits show that the average logic complexity and critical path delay of the programmable FIR filters designed by our proposed algorithm have been reduced by up to 47.81% and 14.32%, respectively over the existing design methods.

VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR) filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA) can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW) and clock cycle (ns) of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW) and clock cycle (ns) are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

An Efficient VLSI Architecture for FIR Filter using Computation Sharing Multiplier

Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite-impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high-performance applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically doing add and shift operation and also targets computation reuse in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA) can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 4-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method.

The Design and Multiplier-Less Realization of Software Radio Receivers With Reduced System Delay

This work studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semi-definite programming (SDP) problem, which allows zero magnitude constraint at /spl omega/=/spl pi/ to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches.

Computation Sharing Programmable FIR Filter for Low-Power and High-Performance Applications

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.

Digitally programmable switched-current FIR filter for low-voltage applications

In this paper, we describe a switched-current (SI) finite-impulse response (FIR) filter, suitable for equalizer architectures. The basic cell of the FIR filter is a SI sample-hold (S/H) circuit, appropriate for low-voltage operation. The programmability of the FIR filter structure is achieved via MOSFET-only current dividers. The FIR filter has been designed and implemented using a 0.8 /spl mu/m CMOS process and operates at a power-supply voltage of 2 V.

On the use of interpolated second-order polynomials for efficient filter design in programmable downconversion

Interpolated second-order polynomials (ISOPs) are proposed to design efficient cascaded integrator-comb (CIC)-based decimation filters for a programmable downconverter. It is shown that some simple ISOPs can effectively reduce the passband droop caused by CIC filtering with little degradation in aliasing attenuation. In addition, ISOPs are shown to be useful for simplifying halfband filters that usually follow CIC filtering. As a result, a modified halfband filter (MHBF) is introduced which is simpler than conventional halfband filters. The proposed decimation filter for programmable downconverter is a cascade of a CIC filter, an ISOP, MHBFs, and a programmable finite impulse response filter. A procedure for designing the decimation filter is developed. In particular, an optimization technique that simultaneously designs the ISOP and programmable FIR filters is presented. Design examples demonstrate that the proposed method leads to more efficient programmable downconverters than existing ones.

Low-power 200-Msps, area-efficient, five-tap programmable FIR filter [in BiCMOS

A two-sample per cycle, programmable five-tap, area-efficient finite-impulse response (FIR) filter for hard-disk drive PRML read channels is presented. The design is optimized for low power, achieving a figure of 6.25 /spl mu/W/MHz with a gate density of 2.3 K, by a combination of algorithmic, architectural, circuit-level, and layout techniques.

An LSI implementation of generalized transversal filters

An LSI implementation of a programmable finite impulse response filter based on a generalized transversal filter structure is described. The overall structure is in the form of tapped and cascaded linear phase FIR subfilters which are processed in parallel. The LSI contains 52 different filters, any one of which can be selected by six external pins. Each filter is equivalent to a conventional filter with about 40-50 filter lengths, and has a maximum sampling rate of 1.11 MHz, the 5.0*5.5 mm/sup 2/ chip was fabricated using 1.5- mu m double-level metal CMOS technology. >

A 30-MHz mixed analog/digital signal processor

A multiplying encoder architecture that is implemented in the design of a mixed analog and digital signal processor is presented. The processor is suitable for performing both high-speed A/D conversion and digital filtering in a single chip. The device can resolve the input with 8 b at 30 Msample/s and perform 28 multiply and 28 add operations per sample under typical conditions. The processor is designed for a 28-tap programmable FIR (finite impulse response) filter with analog input signal which can be used for waveform shaping of the modem to obtain the desired transmission performance for business satellite communication and mobile communication. The chip is fabricated in a 1- mu m double-polysilicon and double-metal CMOS technology. The chip size is 9.73*8.14 mm/sup 2/, and the chip operates with a single +5.0-V power supply. Typical power dissipation is 950 mW; 330 mW is dissipated in analog and 620 mW is in the digital block.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The architectures and design of a 20-MHz real-time DSP chip set

A set of four real-time 20-MHz digital signal processor (DSP) chips has been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video line delay. The circuits were implemented in a 1.5- mu m CMOS process and are fully functional with a 20-MHz clock rate. The processors have reconfigurable windows to allow processing on both one-dimensional and two-dimensional data. The FIR filters can be used in multiprocessor systems to increase the window size and the data precision.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Versatile Spectrum Modification Technique

The spectrum modification technique is a digital procedure for placing the spectrum of any band-limited signal-analog or digital within an arbitrarily chosen set of (nonoverlapping) frequency intervals, the sum of whose lengths is not less than the original bandwidth of the signal. Because it can serve the function of several digital techniques, such as mixing, interpolating, and decimating, and can he realized in a finite impulse response (FIR) filter form, it may be suitably implemented by a programmable FIR filter having a flexible timing scheme. The technique is more computationally efficient for many of its applications than the conventional algorithms it replaces. In the application for which it was developed, it replaced a mixer and the concomitant filtering required to shift a signal spectrum a fraction of its bandwidth and cut the computational rate an order of magnitude.