Programmable Chip Research Articles

Design and Implementation of SoPC based Low power Asynchronous Image Processor

In this paper, design and implementation of SOPC (System on Programmable Chip) based Asynchronous pipelined Discrete Cosine Transform (DCT) is considered. For designing Asynchronous Pipelined DCT, a new approach is proposed. In this approach, Nios II embedded processor is used to control the asynchronous data flow. For implementation of Asynchronous pipelined DCT, Winograd algorithm with 6 stages (Combinational Logic Blocks) of operations is used. The intermittent data between stages are latched by using multiplexer based latches. The completion of each and every stage is informed to the Nios II processor using interrupts. In turn, Nios II processor generates various control signals to pass the intermittent data stored in the multiplexer based latches. In the proposed system, storage of intermittent data is done with multiplexer based latches instead of registers. This leads to minimum power consumption. The system is useful in water marking the patient details on to the patient records to transmit through Internet. The work has been carried out as a part of embedded remote patient monitoring system, in which the measured medical parameters and images of the patients are to be sent to the remote doctor through wired or wireless medium, along with the patient details. The system is implemented in EP1S25F780C5 Altera Stratix FPGA with Nios II embedded processor. Importantly, Nios II processor is also used to validate the DCT & IDCT results by comparing the results with a known set of test vectors.

Design of Video Motion Detect System Based on SOPC

It is very necessary to apply motion detection to video surveillance in order to enhance the performance of system. A new design scheme of video motion detect system based on System On a Programmable Chip is proposed. Two cameras will capture the video data in real-time, and transmitted to DE2_70 development board. After the system which is on a programmable chip based on FPGA processing, the cameras survey whether an illegal personnel is in the range of cameras. The system achieves that two-way video to switch through the switch button. The experimental results show that the SOPC realization of the system design improves the processing speed, and the system also has good flexibility.

Design of Process Controller Based on PCI Interface and CPLD Technology

In order to realize the sensor signal acquisition and analysis of data, according to data acquisition system design ideas of the PCI bus, applying to CPLD complex programmable controller and CH365 interface chip and combined with the actual needs of data collection ,designed a kind of low cost, high speed process controller. CPLD realizes data cache control and the control of reading. This design can gather 16 roads analog signals and real-time pulse signal of 8 roads on the same time, which includes a 16-bit digital output channel and a 32-bit counter, could be used in the real-time control.

A Parallel BP Neural Network Based on the FPGA

This paper, with the analysis of BP neural network learning and execution algorithm on single computer unit, a parallel neural network on many computer units is constructed, a system on programmable chip based on FPGA and uClinux is provided. Because it’s flexibility and reliability, this parallel neural network can be widely used where there is a large quantity of data to be processed. In addition to it, the system based on the SOPC has good versatility and easy to transplant because the reconfiguration of the hardware logic and software system.

Hardware–software optimizations of reconfigurable multi-core processors for floating-point computations of large sparse matrices

State-of-the-art field-programmable gate array (FPGA) technologies have provided exciting opportunities to develop more flexible, less expensive, and better performance floating-point computing platforms for embedded systems. To better harness the full power of FPGAs and to bring FPGAs to more system designers, we investigate unique advantages and optimization opportunities in both software and hardware offered by multi-core processors on a programmable chip (MPoPCs). In this paper, we present our hardware customization and software dynamic scheduling solutions for LU factorization of large sparse matrices on in-house developed MPoPCs. Theoretical analysis is provided to guide the design. Implementation results on an Altera Stratix III FPGA for five benchmark matrices of size up to 7,917 × 7,917 are presented. Our hardware customization alone can reduce the execution time by up to 17.22 %. The integrated hardware---software optimization improves the speedup by an average of 60.30 %.

An Implementation of SOPC-Based Neural Monitoring System

Neurosurgery is an important way to save life in clinical application. As a novel assistant technology for neurosurgery, neural monitoring is used to real-time observe neural state to prevent nerve injury. In this paper, a neural monitoring electronic system based on the methodology of system on programmable chip is presented. On the system, analog and digital circuits are integrated, whereas field-programmable gate array (FPGA) hardware and NIOS II embedded software are co-operated. Some key modules such as preprocessing box, self-adaptive amplification, digital filter, frequency measure, and secure digital card storage are described in detail, and the function of the system is verified by multiform examinations.

Application of DFG Model on SOPC Technology

HW/SW (hardware/software) co-design method based on analysis and optimization of DFG (data flow graphic) model is introduced for SOPC (System on a Programmable Chip) used for digital instrument design in this paper. The method is based on the DFG model of the digital signal process algorithm and implemented with SOPC technology. The DFG model could help designer to divide the function into hardware and software respectively, therefore, the optimizing analysis at system level and circuit level of a SOPC used for portable logic analyzer shows that the DFG model is very useful for not only optimizing architecture and power consumption, but also HW/SW co-design.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

Research on Internet of Things Based on SOPC

An Internet of things system using Cyclone EP2C8 FPGA chip of Altera is designed and researched in this paper, which integrated NiosII soft-core processor, memory, functional interfaces with SOPC (system on a programmable chip) technology. The μC/OS-II embedded operating system is transplanted here to realize the network communication through driving the network chip. Simultaneously, the message stored in card can be correctly identified, recorded, added up by RFID technology, and sent to internet according to the requirement of communication. Thus, the internet of things function is realized.

An Accurate Fractional Period Delay Generation System

An all-digital technique is proposed for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A subsampling technique-based delay measurement unit (DMU) capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The proposed delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. Up to 40 improvement in accuracy is demonstrated for a commercial programmable delay generator chip. The time-precision trade-off feature of the DMU is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter. Measurement results from a high-end oscilloscope also validate the effectiveness of the proposed system in improving accuracy.

Field programmable gate array/system on a programmable chip-based implementation of model predictive controller

To improve the on-line computational performance of model predictive control (MPC) for fast systems and/or embedded systems, this study proposes a novel scheme for the MPC controller implementation based on field programmable gate array (FPGA) and system on a programmable chip (SOPC) technology. A Nios II processor clocked at 150 MHz is embedded into the FPGA chip. A C/C++ model of the MPC algorithm which is run in the Nios II processor is created. The dual method is adopted to solve the quadratic programming (QP) problem. Based on FPGA and dSPACE®, a rapid prototyping platform is introduced to test and verify the function and computational performance of the MPC controller. Real-time simulation results of controlling a throttle model show that a reasonable size of constrained MPC controller can be implemented on the used RCIII FPGA board.

Whirlpool SoPC Implementation - Hardware/Software Co-Design Example

Whirlpool SoPC Implementation - Hardware/Software Co-Design Example The aim of this work was to design a System on Programmable Chip (SoPC), that implements the Whirlpool Hash Function (WHF) algorithm. An assumption of the project was to use an embedded soft-processor NIOS II controlling the whole system, which functionality was extended by a custom logic in order to improve the used algorithm efficiency. This paper presents the Whirlpool Hash Function realized in several SoPC configurations, which differ in implementation complexity and performance.

Hardware Software Co-Design for JPEG Encoder Test Bench

This paper presents a hardware/software (HW/SW) co-design approach using System On a Programmable Chip (SOPC) technique to achieve Joint Photographic Experts Group (JPEG) algorithm. It firstly introduces JPEG image compression technology and the system architecture. Then the hardware/software design process of JPEG encoder test bench is introduced. It focuses on using the characteristics of Field-Programmable Gate Array (FPGA) structure to achieve JPEG algorithm including the improved Discrete Cosine Transform (DCT), and Nios II embedded processor of customizable characteristics, translating image acquisition, JPEG image compression and Thin Film Transistor Liquid Crystal Display (TFT-LCD) controller into user-defined modules according to Altera Avalon bus requirements with the SOPC Builder, where the user-defined module can be added to the system under the control of soft-core Nios II Embedded. Finally, the whole system is verified on a single FPGA chip. The experimental results shows the advantages of JPEG algorithm as a FPGA hardware module includes low power consumption, high image quality, low production costs and stable performance. There’s a very great practical significance to reduce costs and improve image processing speed.

Design and implementation of a real time and train less eye state recognition system

Eye state recognition is one of the main stages of many image processing systems such as driver drowsiness detection system and closed-eye photo correction. Driver drowsiness is one of the main causes in the road accidents around the world. In these circumstances, a fast and accurate driver drowsiness detection system can prevent these accidents. In this article, we proposed a fast algorithm for determining the state of an eye, based on the difference between iris/pupil color and white area of the eye. In the proposed method, vertical projection is used to determine the eye state. This method is suitable for hardware implementation to be used in a fast and online drowsiness detection system. The proposed method, along with other needed preprocessing stages, is implemented on Field Programmable Gate Array chips. The results show that the proposed low-complex algorithm has sufficient speed and accuracy, to be used in real-world conditions.

Design and Implementation of a Single Chip Multi-Waveform Signal Generator Based on SOPC Design Methodology

This work presents a highly integrated multi-functional, multi-waveform signal generator which can generate various waveforms, with digital controller inside to adapt embedded and low power applications. The proposed system uses Nios II, a reconfigurable, programmable and optimizable soft-core embedded CPU together with modern EDA tools to accomplish system HW/SW co-design and implementation. Utilizing characteristics of Nios II, we put together core and peripheral logical units that system needs and implant them into a single FPGA chip, then uses the Avalon bus to connect peripheral modules (such as function switch buttons and 7-segment LED display units) to Nios II's Avalon bus main port (instruction and data control port). The realized system is flexible to reduce, extend, with low power consumption, and has System on Programmable Chip (SOPC) function which means the system’s software and hardware is online programmable.

Hardware implementation and validation of the fast variable block size motion estimation architecture for H.264/AVC

Block matching motion estimation is the heart of video coding system. It leads to a high compression ratio, whereas it is time consuming and calculation intensive. Many fast search block matching motion estimation algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose an efficient hardware architecture of the fast line diamond parallel search (LDPS) algorithm with variable block size motion estimation (VBSME) for H.264/AVC video coding system. The design is described in VHDL language, synthesized to Altera Stratix III FPGA and to TSMC 0.18μm standard-cells. The throughput of the hardware architecture reaches a processing rate up to 78 millions of pixels per second at 83.5MHz frequency clock and uses only 28kgates when mapped to standard-cells. Finally, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded video system.

An FPGA Implementation Of Hearing Aids based on Wavelet-Packets

Advances in digital signal processing and microelectronics have led to the development of superior digital hearing aids for ameliorating severe defects of hearing. The progress in field programmable gate arrays (FPGA) technology, especially for miniaturized system applications, allowed increasing sophisticated features to be built for better sound reproduction, keeping small size and low power consumption of the devices. In this paper the recent trend of combining interconnects of FPGAs with embedded microprocessors and related peripherals to form a complete system on a programmable chip is employed for the design of digital hearing aids. Wavelet packet transform is applied for speech compensation of the hearing loss. The wavelet packet module is described in VHDL, implemented on FPGA and then added as a peripheral to the processor system. The embedded software processor used is the MicroBlaze soft core processor. The chip used is Digilent XUP II Virtex-II Pro system FPGA containing audio codec LM4550. The features of the design are small area and fast processing and low cost.

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core Systems on a programmable chip (MCSoPC). Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software and/or hardware, that communicate over a seamless interface. Redsharc incorporates two on-chip networks that directly implement the API to support high-performance systems with numerous hardware kernels. This paper documents the API, describes the common infrastructure, and quantifies the performance of a complete implementation. Furthermore, the overhead, in terms of resource utilization, is reported along with the ability to integrate hard and soft processor cores with purely hardware kernels being demonstrated.

A Multi-Objective Optimization Genetic Algorithm for SOPC Hardware-Software Partitioning

Hardware-software partitioning is the key technology in hardware-software co-design; the results will determine the design of system directly. Genetic algorithm is a classical search algorithm for solving such combinatorial optimization problem. A Multi-objective genetic algorithm for hardware-software partitioning is presented in this paper. This method can give consideration to both system performance and indicators such as time, power, area and cost, and achieve multi-objective optimization in system on programmable chip (SOPC). Simulation results show that the method can solve the SOPC hardware-software partitioning problem effectively.