Design and Implementation of SoPC based Low power Asynchronous Image Processor

Abstract

In this paper, design and implementation of SOPC (System on Programmable Chip) based Asynchronous pipelined Discrete Cosine Transform (DCT) is considered. For designing Asynchronous Pipelined DCT, a new approach is proposed. In this approach, Nios II embedded processor is used to control the asynchronous data flow. For implementation of Asynchronous pipelined DCT, Winograd algorithm with 6 stages (Combinational Logic Blocks) of operations is used. The intermittent data between stages are latched by using multiplexer based latches. The completion of each and every stage is informed to the Nios II processor using interrupts. In turn, Nios II processor generates various control signals to pass the intermittent data stored in the multiplexer based latches. In the proposed system, storage of intermittent data is done with multiplexer based latches instead of registers. This leads to minimum power consumption. The system is useful in water marking the patient details on to the patient records to transmit through Internet. The work has been carried out as a part of embedded remote patient monitoring system, in which the measured medical parameters and images of the patients are to be sent to the remote doctor through wired or wireless medium, along with the patient details. The system is implemented in EP1S25F780C5 Altera Stratix FPGA with Nios II embedded processor. Importantly, Nios II processor is also used to validate the DCT & IDCT results by comparing the results with a known set of test vectors.