A data communications network (50) for magnetic resonance imaging (MRI) systems provides characteristics ideal for low noise operation and low cost at speeds as high as 1 Mbytes/sec and provides a serial data bus for performing medium speed control and data acquisition functions. System architecture is extremely versatile and also low in cost. Each node (400) of the communications system (50) may be provided with an interface implemented with electronically programmable array logic (EPLD) applications specific integrated circuits (ASIC) (406, 408, 410, 412) with 1800 equivalent gates per CMOS integrated circuit. The resulting chip set (406, 408, 410, 412) is self clocking (no local oscillator is required) and nominally provides 20 bits of latched output and input with parity checking in a four-chip set configuration. A minimal two-chip set (406, 410) configuration can be used for nodes (400) that need only 4 bits of latched input and output data (while still supporting parity checking). Different types of peripherals can easily be accommodated, and the bus (360) is self configuring.