Program-driven Simulation Research Articles

단방향 이중연결 CC-NUMA 시스템의 동적 부하 대응 경로 설정 기법

높은 클럭으로 동작하는 고속의 프로세서를 다수 이용한 다중프로세서 시스템 성능은 프로세서 자체의 성능보다 상호연결망의 트랜잭션 처리 능력 및 지연에 의하여 큰 영향을 받게 된다. 따라서 상호연결망의 성능은 대역폭 및 지연시간 측면으로 시스템 성능에 큰 비중을 차지한다. 단방향 이중 연결을 이용한 CC-NUMA 구조는 이중 연결을 이용한 대역폭 증가효과와 고속 단방향 링크를 이용한 적은 지연시간으로 인하석 고성능 시스템에서 많이 채용되고 있다. 한편, 이중 연결구조로 인하여 시스템의 상호연결망의 최단 경로는 단일하게 형성되지 않으며, 여러 개의 최단 경로가 구성될 수 있다. 그러나 실제 응용프로그램을 수행할 때, 동일한 홉 수를 나타내는 경로일지라 하더라도 각 연결 링크의 부하 및 경쟁에 따른 지연 시간의 차이를 나타내게 되며, 만일 노드간의 트랜잭션 전달 경로가 정적으로 구성되어 있을 경우, 실제 프로그램의 수행에서 균일하지 못한 연결 링크 부하에 따른 지연 시간의 차이가 나타날 수 있음을 의미한다. 이는 곧 고속의 상호연결망 전체의 대역폭을 균일하게 사용하지 못함으로 나타나는 부가적 지연 시간으로 볼 수 있으며, 이로 인한 응용 프로그램의 수행 성능이 저하될 수 있음을 의미한다. 본 논문은 기존 연구된 단방향 이중 연결을 이용한 CC-NUMA 시스템에서, 노드간 트랜잭션 전달 경로가 정 적으로 구성될 경 우 발생될 수 있는 성능 저하를 평가하고, 정적 경로와 동일한 홉 수의 경로를 나타내며 링크 부하에 따라서 동적으로 전달되도록 부하에 따르는 동적 경로 설정 방법을 제시하였다. 논문에서 제시하는 방법은 기존 경로설정 방법에 대하여 동일한 홉 수를 나타내며, 링크 부하에 따라서 동적으로 경로를 설정함으로써 실시간 경로 분배가 자연스럽게 이루어지도록 하였고, 링크 경쟁을 완화함으로써 보다 균일한 링크 사용을 나타냈고, 링크 획득 실패로 인한 지 연시간을 감소시켰다. 프로그램 구동 시뮬레이션을 통한 성능 검증 결과, 논문에서 제시한 동적경로 설정 방법은 기존 정적 경로 설정 방법에 비해 링크점유시간 편차가 <TEX>$1{\~}10\%$</TEX> 낮게 나타났고, 링크의 획득 실패 횟수가 <TEX>${\~}3\%$</TEX> 감소하였으며, 그 결과 <TEX>$1{\~}6\%$</TEX>의 수행 시간 감소를 나타냈다. Throughput and latency of interconnection network are important factors of the performance of multiprocessor systems. The dual-link CC-NUMA architecture using point-to-point unidirectional link is one of the popular structures in high-end commercial systems. In terms of optimal path between nodes, several paths exist with the optimal hop count by its native multi-path structure. Furthermore, transaction latency between nodes is affected by congestion of links on the transaction path. Hence the transaction latency may get worse if the transactions make a hot spot on some links. In this paper, I propose a dynamic transaction routing algorithm that maintains the balanced link utilization with the optimal path length, and I compare the performance with the fixed path method on the dual-link CC-NUMA systems. By the proposed method, the link competition is alleviated by the real-time path selection, and consequently, dynamic transaction algorithm shows a better performance. The program-driven simulation results show <TEX>$1{\~}10\%$</TEX> improved fluctuation of link utilization, <TEX>$1{\~}3\%$</TEX> enhanced acquirement of link, and <TEX>$1{\~}6\%$</TEX> improved system performance.

Reducing Control Latency in Distributed Shared-Memory Multiprocessor Systems Using Fuzzy Logic Prediction

Communication latency is a major limiting factor for scalability in distributed shared-memory multiprocessor systems. It can be generally reduced by predicting the communication traffic in a system connected through a reconfigurable interconnection network. The State Sequence Routing (SSR) control-based algorithm uses a set of predicted paths to do an anticipatory reconfiguration for the interconnection network (IN) in such a way as to include the set of predicted paths in the current state sequence. By reducing the control latency and thus the overall execution time of a parallel application, we can increase the network size and therefore improve the scalability. In this article we use a fuzzy inference system (FIS) to perform online prediction of the paths between processors and memory units. The fuzzy system uses as input the memory access patterns across a set of time-windows to predict the communication paths within the next time window. Hence, the prediction is based on the locality inherent in the memory access patterns for all processors across the network. To investigate the effectiveness of our approach, we perform several simulation experiments using a program-driven simulator. Based on the results of experiments, our algorithm reduces the communication latency and thus the overall execution time according to the locality inherent in the communication traffic across the network using as little resources as possible in terms of the length of the state sequence router and the size of the rule base.

다중 프로그램 환경에 적합한 이중 연결 CC-NUMA 시스템

다중 프로세서 시스템에서 여러 개의 프로그램이 동시에 수행될 경우의 프로그램 수행 성능은 각 프로세스를 어떠한 물리적 위치의 프로세서에 할당하여 수행하는가에 따라 다르게 나타난다. 일반적으로 시공간적으로 인접한 프로세서에 동일 프로그램의 프로세서를 할당할 경우 프로세스간 통신비용이 절감되므로 가장 효율적인 결과를 얻을 수 있다. 그러나 프로세스를 할당하는 운영체제는 이와 같은 친화성을 고려하기 위하여 부가적인 처리를 필요로 하며, 실제 수행시 각 프로그램은 독립적으로 수행되므로, 여러 프로그램으로부터 발생한 프로세스를 할당하는 방법은 많은 계산을 필요로 한다. 이중 링 구조의 CC-NUMA 시스템의 경우 특히 다수의 공유 메모리 접근에 의한 많은 트랜잭션이 발생하며, 연결망 부하의 불균등에 따른 병목 현상을 나타내므로, 프로세스의 할당 정책에 따라서 큰 성능 차이를 나타내게 된다. 본 논문은 규일한 연결망 부하특성을 나타내며, 프로세스 할당 정책을 필요로 하지 않는 CC-NUMA 시스템을 제시한다. 논문에서 제시하는 구조는 이중 링 구조와 동일한 연결망 비용을 나타내며, 건너뜀 연결을 이용한 균등한 부하 분배를 수행함으로써 프로세스 할당 정책의 유무와 무관한 성능을 보이다. 프로그램 구동 시뮬레이션을 통한 검증 결과 시스템은 이중 링 구조의 CC-NUMA 시스템에 비하여 1.5배의 성능 개선을 나타냈다. Under the multiprogrammed situation, the performance of multiprocessor system is affected by the process allocation policy of the operating systems. The lowest communication cost can be achieved when the related processes positioned to the adjacent processors. While the effective allocation is quite difficult to the real situation, and the processing of the allocation policy consumes some computation time. The dual-ring CC-NUMA systems exhibit a quite performance difference according to the process a1location policy due to a lot of unbalanced memory transactions on the interconnection networks. In this paper, I propose a load balanced dual-link CC-NUMA system that does not requires the processes allocation policy. By the program-driven simulation results. the proposed system shows no remarkable difference according to the allocation policy while the dual-ring systems shows 10％ performance improvement by the process allocation. In addition, the proposed system outperforms the dual~ring systems about 1.5 times.

A performance evaluation of cache injection in bus-based shared memory multiprocessors

Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small- to medium-scale parallel machines today. In these systems, the high memory latency poses the major hurdle in achieving high performance. One way to cope with this problem is to use various techniques for tolerating high memory latency. Software-controlled cache prefetching and data forwarding are two widely used techniques for tolerating high memory latency in scalable cache-coherent shared memory multiprocessors. However, some previous studies have shown that these techniques are not so effective in bus-based shared memory multiprocessors. In this paper, we propose a novel software-controlled technique called cache injection, which combines consumer and producer initiated approach, and broadcasting nature of bus. Performance evaluation based on program-driven simulation and a set of scientific applications and test benchmarks shows that cache injection is highly effective in reducing misses and bus traffic.

On-chip Multiprocessor with Simultaneous Multithreading

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of 1 a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multiprocessor designs.

Techniques for Improving Performance of Hybrid Snooping Cache Protocols

Bus-based multiprocessors constitute a cost-effective class of shared-memory multiprocessors. Private caches are the key to an efficient utilization of the shared bus, and most such systems use a write-invalidate cache-coherence protocol to keep the caches coherent. Two important factors that limit the performance of the system are cache misses that lead to long-latency reads and bus congestion because of read misses and coherence traffic. While hybrid write-invalidate/write-update snooping protocols lead to fewer read misses than write-invalidate protocols, previous studies have shown them to be incapable of providing consistent performance improvements because of heavily increased coherence traffic. In this paper, we analyze how the deficiencies of hybrid snooping protocols can be dramatically reduced by using write caches and read snarfing (also called read-broadcast) under release consistency. Our performance evaluation is based on program-driven simulation and a set of five scientific applications with different sharing behaviors including migratory sharing as well as producer–consumer sharing. We show that one of the evaluated hybrid protocols, extended with write caches as well as read snarfing, manages to reduce the number of coherence misses by between 83 and 93% as compared to a write-invalidate protocol for all five applications in this study. In addition, the number of bus transactions is reduced substantially. However, we also show that read snarfing and hybrid snooping protocols might lead to higher cache occupancy because of increased sharing. Because of the small implementation cost of the hybrid protocol and the two extensions, we believe the combination to be an effective approach to boosting the performance of bus-based multiprocessors.

Boosting the performance of hybrid snooping cache protocols

Previous studies of bus-based shared-memory multiprocessors have shown hybrid write-invalidate/write-update snooping protocols to be incapable of providing consistent performance improvements over write-invalidate protocols. In this paper, we analyze the deficiencies of hybrid snooping protocols under release consistency, and show how these deficiencies can be dramatically reduced by using write caches and read snarfing.Our performance evaluation is based on program-driven simulation and a set of five scientific applications with different sharing behaviors including migratory sharing as well us producer-consumer sharing. We show that a hybrid protocol, extended with write caches as well as read snarfing, manages to reduce the number of coherence misses by between 83% and 95% as compared to a write-invalidate protocol for all five applications in this study. In addition, the number of bus transactions is reduced by between 36% and 60% for four of the applications and by 9% for the fifth application. Because of the small implementation cost of the hybrid protocol and the two extensions, we believe that this combination is an effective approach to boost the performance of bus-based multiprocessors.

SM-prof

Cache misses due to coherence actions are often the major source for performance degradation in cache coherent multiprocessors. It is often difficult for the programmer to take cache coherence into account when writing the program since the resulting access pattern is not apparent until the program is executed.SM-prof is a performance analysis tool that addresses this problem by visualising the shared data access pattern in a diagram with links to the source code lines causing performance degrading access patterns. The execution of a program is divided into time slots and each data block is classified based on the accesses made to the block during a time slot. This enables the programmer to follow the execution over time and it is possible to track the exact position responsible for accesses causing many cache misses related to coherence actions.Matrix multiplication and the MP3D application from SPLASH are used to illustrate the use of SM-prof. For MP3D, SM-prof revealed performance limitations that resulted in a performance improvement of over 75%.The current implementation is based on program-driven simulation in order to achieve non-intrusive profiling. If a small perturbation of the program execution is acceptable, it is also possible to use software tracing techniques given that a data address can be related to the originating instruction.

An adaptive cache coherence protocol optimized for migratory sharing

Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a write-invalidate protocol result in invalidation actions that could be eliminated. For this type of sharing, called migratory sharing, each processor typically causes a cache miss followed by an invalidation request which could be merged with the preceding cache-miss request. In this paper we propose an adaptive protocol that invokes this optimization dynamically for migratory blocks. For other blocks, the protocol works as an ordinary write-invalidate protocol. We show that the protocol is a simple extension to a write-invalidate protocol. Based on a program-driven simulation model of an architecture similar to the Stanford DASH, and a set of four benchmarks, we evaluate the potential performance improvements of the protocol. We find that it effectively eliminates most single invalidations which improves the performance by reducing the shared access penalty and the network traffic.

Educational tool for design of parallel processing systems

A software package which can be used as an educational tool for the design of a subset of parallel processing architecture (PPA) systems is presented. A user-friendly interface guides the user through the different steps involved in specifying and emulating PPA systems using program-driven simulation. The user can choose any of the following PPA systems categorised according to Flynn's taxonomy: MISD (multiple instruction single data), SIMD (single instruction multiple data) and MIMD (multiple instruction multiple data). Workload and scheduler specifications can be defined by the user. The evaluation model is based on the queuing theory for the modelling and simulation of PPA systems. The simulation program is based on a linked list structure to represent events. The package includes HELP and ERROR LOG utilities, and provides graphical illustrations of the results and performance indices.

A program-driven simulation model of an MIMD multiprocessor

A simulation model that supports very accurate modeling of multiprocessors with a hierarchical, packet-switched interconnection network and private caches is explored. The simulation system contains workload simulators and a memory system simulator. The workload simulators are program-driven, i.e. they actually execute programs. The time unit of the simulator is the time between two consecutive memory references from the processors. The performance of the simulation model, although acceptable, could be improved using a trace-driven approach. The author shows that results obtained from trace-driven simulation methods in the course of multiprocessor performance evaluation are generally not valid. Furthermore, he shows that in the evaluation of certain processor architectural features, such as non-blocking architectures, the program-driven approach is necessary. >

A program-driven simulation model of an MIMD multiprocessor

A program-driven simulation model of an MIMD multiprocessor